Patents by Inventor Richard Austin
Richard Austin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200226405Abstract: Methods for detecting digital or physical tampering of an imaged physical credential include the actions of: receiving a digital image representing a physical credential having one or more high value regions, the digital image including an array of pixels; processing the digital image with a tamper detector to generate an output corresponding to an intrinsic characteristic of the digital image, the tamper detector configured to perform a pixel-level analysis of the high value regions of the digital image with respect to a predetermined tampering signature; and determining, based on the output from the tamper detector, whether the digital image has been digitally tampered with.Type: ApplicationFiled: January 13, 2020Publication date: July 16, 2020Inventors: Richard Austin Huber, JR., Satya Prakash Mallick, Matthew William Flagg, Koustubh Sinhal
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Patent number: 10534971Abstract: Methods for detecting digital or physical tampering of an imaged physical credential include the actions of: receiving a digital image representing a physical credential having one or more high value regions, the digital image including an array of pixels; processing the digital image with a tamper detector to generate an output corresponding to an intrinsic characteristic of the digital image, the tamper detector configured to perform a pixel-level analysis of the high value regions of the digital image with respect to a predetermined tampering signature; and determining, based on the output from the tamper detector, whether the digital image has been digitally tampered with.Type: GrantFiled: October 13, 2017Date of Patent: January 14, 2020Assignee: ID Metrics Group IncorporatedInventors: Richard Austin Huber, Jr., Satya Prakash Mallick, Matthew William Flagg, Koustubh Sinhal
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Publication number: 20190377970Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for an active lighting system. In one aspect, a method includes receiving a first image of the physical document having a first glare signature and a second image of the physical document having a second glare signature that is different from the first glare signature; determining a first glare map of the first image and a second glare map of the second image; comparing the first glare map to the second glare map; and generating the digital image based on the comparison of the first and second glare maps.Type: ApplicationFiled: June 11, 2019Publication date: December 12, 2019Inventors: Richard Austin Huber, JR., Matthew William Flagg, Satya Prakash Mallick
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Patent number: 10499499Abstract: A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. A patterned hydrophobic layer defines the locations of the printed dots of the devices. The devices in each group are connected in parallel so that each group acts as a single device. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.Type: GrantFiled: January 11, 2018Date of Patent: December 3, 2019Assignee: Nthdegree Technologies Worldwide Inc.Inventors: William Johnstone Ray, Richard Austin Blanchard, Mark David Lowenthal, Bradley Steven Oraw
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Patent number: 10497672Abstract: Active LEDs have a control transistor in series with an LED and have a top electrode, a bottom electrode, and a control electrode. The active LEDs are microscopic and dispersed in an ink. A substrate has column lines, and the active LEDs are printed at various pixel locations so the bottom electrodes contact the column lines. A hydrophobic mask defines the pixel locations. Due to the printing process, there are different numbers of active LEDs in the various pixel locations. Row lines and control lines contact the top and control electrodes so that the active LEDs in each single pixel location are connected in parallel. If the LEDs emit blue light, red and green phosphors are printed over various pixel locations to create an ultra-thin color display. Any active LED may be addressed using row and column addressing, and the brightness may be controlled using the control lines.Type: GrantFiled: October 6, 2017Date of Patent: December 3, 2019Assignee: Nthdegree Technologies Worldwide Inc.Inventors: William Johnstone Ray, Mark David Lowenthal, Richard Austin Blanchard, Lixin Zheng, Xiaorong Cai, Bradley S. Oraw
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Patent number: 10439815Abstract: In general, one innovative aspect of the subject matter described in this specification may be embodied in methods that may include validating user data pages extracted from a digital identification in circumstances where a user device that includes the digital identification is either unavailable or presently lacks network connectivity. For instance, an authorized device may be used to extract user data pages from the digital identification by either exchanging communications with the user device using a proximity-based data exchange protocol, or by using a physical identification card to identify the digital identification on a user record. The user data pages may then be validated by comparing checksums associated with user data pages against the checksums within the user record, and decrypting the user data pages using a decryption key that is variably designated by a security status assigned to the digital identification.Type: GrantFiled: December 30, 2015Date of Patent: October 8, 2019Assignee: MorphoTrust USA, LLCInventors: Daniel Poder, Richard Austin Huber
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Patent number: 10432618Abstract: In general, one innovative aspect of the subject matter described in this specification may be embodied in methods that may include verifying a digital identification using embedded encrypted user credential data that is not viewable to human eyes within the digital identification. For instance, the embedded encrypted user credential data may be variably encrypted by an encryption key that is designated by a security status assigned to the digital identification. The embedded encrypted user credential data may be extracted using an authorized device and decrypted using a decryption key that is associated with the encryption key designated by the security status. The decrypted user credential data may then be used to verify user information included in the digital identification.Type: GrantFiled: December 31, 2015Date of Patent: October 1, 2019Assignee: MorphoTrust USA, LLCInventors: Daniel Poder, Richard Austin Huber
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Patent number: 10412833Abstract: A programmable circuit includes an array of printed groups of microscopic transistors or diodes having pn junctions. The devices are pre-formed and printed as an ink and cured. The devices have a proper orientation and a reverse orientation after settling on a conductor layer. The devices are connected in parallel within small groups. To neutralize the reverse-oriented devices, a sufficient voltage is applied across the parallel-connected diodes to forward bias only the devices having the reverse orientation. This causes a sufficient current to flow through each of the reverse-orientated devices to destroy an electrical interface between an electrode of the devices and the conductor layer to create an open circuit, such that those devices do not affect a rectifying function of the devices in the group having the proper orientation. An interconnection conductor pattern may then interconnect the groups to form complex logic circuits.Type: GrantFiled: September 19, 2018Date of Patent: September 10, 2019Assignee: Nthdegree Technologies Worldwide Inc.Inventors: Richard Austin Blanchard, William Johnstone Ray
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Patent number: 10331291Abstract: In general, one innovative aspect of the subject matter described in this specification may be embodied in methods that include verifying a digital identification using visual indicators displayed to an authorized user. For instance, the visual indicators may be a set of graphical representations that are variably selected to be displayed on the digital identification. The visual indicator information may be provided to the authorized user to enable verification of the digital identification without any additional detector devices.Type: GrantFiled: December 31, 2015Date of Patent: June 25, 2019Assignee: Morpho Trust USA, LLCInventors: Daniel Poder, Richard Austin Huber
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Patent number: 10257495Abstract: In general, one innovative aspect of the subject matter described in this specification may be embodied in methods that include generating a three-dimensional composite image of a user from a set of two dimensional facial images. For instance, a depth map may initially be generated for each of the two dimensional facial images based on depth information. The depth maps may be used to identify matching elements that are used to combine multiple two-dimensional images. The generated three-dimensional composite image may then be displayed on a digital identification of a user device. In some instances, the rendering of the three-dimensional composite image on the user device may be adjusted based on tilting motions.Type: GrantFiled: December 31, 2015Date of Patent: April 9, 2019Assignee: MorphoTrust USA, LLCInventors: Daniel Poder, Brian Martin, Richard Austin Huber
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Publication number: 20190098759Abstract: A programmable circuit includes an array of printed groups of microscopic transistors or diodes having pn junctions. The devices are pre-formed and printed as an ink and cured. The devices have a proper orientation and a reverse orientation after settling on a conductor layer. The devices are connected in parallel within small groups. To neutralize the reverse-oriented devices, a sufficient voltage is applied across the parallel-connected diodes to forward bias only the devices having the reverse orientation. This causes a sufficient current to flow through each of the reverse-orientated devices to destroy an electrical interface between an electrode of the devices and the conductor layer to create an open circuit, such that those devices do not affect a rectifying function of the devices in the group having the proper orientation. An interconnection conductor pattern may then interconnect the groups to form complex logic circuits.Type: ApplicationFiled: September 19, 2018Publication date: March 28, 2019Inventors: Richard Austin Blanchard, William Johnstone Ray
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Publication number: 20180132347Abstract: A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. A patterned hydrophobic layer defines the locations of the printed dots of the devices. The devices in each group are connected in parallel so that each group acts as a single device. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.Type: ApplicationFiled: January 11, 2018Publication date: May 10, 2018Inventors: William Johnstone Ray, Richard Austin Blanchard, Mark David Lowenthal, Bradley Steven Oraw
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Publication number: 20180114775Abstract: Active LEDs have a control transistor in series with an LED and have a top electrode, a bottom electrode, and a control electrode. The active LEDs are microscopic and dispersed in an ink. A substrate has column lines, and the active LEDs are printed at various pixel locations so the bottom electrodes contact the column lines. A hydrophobic mask defines the pixel locations. Due to the printing process, there are different numbers of active LEDs in the various pixel locations. Row lines and control lines contact the top and control electrodes so that the active LEDs in each single pixel location are connected in parallel. If the LEDs emit blue light, red and green phosphors are printed over various pixel locations to create an ultra-thin color display. Any active LED may be addressed using row and column addressing, and the brightness may be controlled using the control lines.Type: ApplicationFiled: October 6, 2017Publication date: April 26, 2018Inventors: William Johnstone Ray, Mark David Lowenthal, Richard Austin Blanchard, Lixin Zheng, Xiaorong Cai, Bradley S. Oraw
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Publication number: 20180107887Abstract: Methods for detecting digital or physical tampering of an imaged physical credential include the actions of: receiving a digital image representing a physical credential having one or more high value regions, the digital image including an array of pixels; processing the digital image with a tamper detector to generate an output corresponding to an intrinsic characteristic of the digital image, the tamper detector configured to perform a pixel-level analysis of the high value regions of the digital image with respect to a predetermined tampering signature; and determining, based on the output from the tamper detector, whether the digital image has been digitally tampered with.Type: ApplicationFiled: October 13, 2017Publication date: April 19, 2018Inventors: Richard Austin Huber, JR., Satya Prakash Mallick, Matthew William Flagg, Koustubh Sinhal
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Patent number: 9913371Abstract: A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. A patterned hydrophobic layer defines the locations of the printed dots of the devices. The devices in each group are connected in parallel so that each group acts as a single device. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.Type: GrantFiled: January 13, 2017Date of Patent: March 6, 2018Assignee: Nthdegree Technologies Worldwide Inc.Inventors: William Johnstone Ray, Richard Austin Blanchard, Mark David Lowenthal, Bradley Steven Oraw
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Publication number: 20180050004Abstract: The present invention relates to uses of and methods of treatment with cystathionine. In one embodiment, cystathionine reduces the development of toxin-induced liver and/or kidney disease induced by homocystinuria and/or acute nephropathy. In one embodiment, a cystathionine synthesis inhibitor is administered to increase tumor cell apoptosis and/or increase the efficacy of chemotherapeutic treatment. More particularly, cystathionine can protect cells against toxin-induced cellular apoptosis and/or cystathionine synthesis inhibitors can increase neuroblastoma cell kill rates during chemotherapy.Type: ApplicationFiled: November 1, 2017Publication date: February 22, 2018Inventors: KENNETH MACLEAN, RICHARD AUSTIN
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Patent number: 9887425Abstract: A plurality of batteries is printed on a flexible substrate, where each battery may output the same voltage, such as about 1.5 volts. Batteries in a first subset are connectable in parallel by controllable switches to control the maximum current that can be delivered to a load. Batteries in a second subset are also connectable in parallel by additional controllable switches to control the maximum current that can be delivered to the load. Another group of switches can either connect the two subsets of batteries in series, to generate 3 volts, or connect the subsets in parallel to increase the maximum current. Additional subsets of batteries and their associated switches may be further connected to increase the voltage and current. The power supply may be standardized and configured by the user for a particular load, such as a sensor for a medical skin patch.Type: GrantFiled: January 12, 2016Date of Patent: February 6, 2018Assignee: Printed Energy Pty. Ltd.Inventors: Richard Austin Blanchard, William Johnstone Ray, Mark David Lowenthal, Thomas Frederick Soules, Vera Lockett
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Publication number: 20170135214Abstract: A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. A patterned hydrophobic layer defines the locations of the printed dots of the devices. The devices in each group are connected in parallel so that each group acts as a single device. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.Type: ApplicationFiled: January 13, 2017Publication date: May 11, 2017Inventors: William Johnstone Ray, Richard Austin Blanchard, Mark David Lowenthal, Bradley Steven Oraw
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Publication number: 20170125372Abstract: A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. The devices in each group are connected in parallel so that each group acts as a single device. In one embodiment, about 10 devices are contained in each group so the redundancy makes each group very reliable. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.Type: ApplicationFiled: January 18, 2017Publication date: May 4, 2017Inventors: William Johnstone Ray, Richard Austin Blanchard, Mark David Lowenthal, Bradley Steven Oraw
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Patent number: 9577007Abstract: An LED module is disclosed containing an integrated driver transistor (e.g, a MOSFET) in series with an LED. In one embodiment, LED layers are grown over a substrate. The transistor regions are formed over the same substrate. After the LED layers, such as GaN layers, are grown to form the LED portion, a central area of the LED is etched away to expose a semiconductor surface in which the transistor regions are formed. A conductor connects the transistor in series with the LED. Another node of the transistor is electrically coupled to an electrode on the bottom surface of the substrate. In one embodiment, an anode of the LED is connected to one terminal of the module, one current carrying node of the transistor is connected to a second terminal of the module, and the control terminal of the transistor is connected to a third terminal of the module.Type: GrantFiled: September 28, 2015Date of Patent: February 21, 2017Assignee: Nthdegree Technologies Worldwide Inc.Inventors: Richard Austin Blanchard, Bradley Steven Oraw