Abstract: Techniques herein provide methods for depositing spin-on metal materials for creating metal hard mask (MHM) structures without voids in the deposition. This includes effective spin-on deposition of TiOx, ZrOx, SnOx, HFOx, TaOx, et cetera. Such materials can help to provide differentiation of material etch resistivity for differentiation. By enabling spin-on metal hard mask (MHM) for use with a multi-line layer, a slit-based or self-aligned blocking strategy can be effectively used. Techniques herein include identifying a fill material to fill particular openings in a given relief pattern, modifying a surface energy value of surfaces within the opening such that a contact angle value of an interface between the fill material in liquid form and the sidewall or floor surfaces enables gap-free or void-free filling.

Abstract: A method includes forming at least one fin on a semiconductor substrate. A hard mask layer is formed above the fin. A first directed self-assembly material is formed above the hard mask layer. The hard mask layer is patterned using a portion of the first directed self-assembly material as an etch mask to expose a portion of the top surface of the fin. A substantially vertical nanowire is formed on the exposed top surface. At least one dimension of the substantially vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material.

Abstract: Methods for directed self-assembly (DSA) using chemoepitaxy in the design and fabrication of integrated circuits are disclosed herein. An exemplary method includes forming an A or B-block attracting layer over a base semiconductor layer, forming a trench in the A or B-block attracting layer to expose a portion of the base semiconductor layer, and forming a neutral brush or mat or SAMs layer coating within the trench and over the base semiconductor layer. The method further includes forming a block copolymer layer over the neutral layer coating and over the A or B-block attracting layer and annealing the block copolymer layer to form a plurality of vertically-oriented, cylindrical structures within the block copolymer layer.

Abstract: Methods for fabricating integrated circuits are provided. One method includes decomposing a master pattern layout for a semiconductor device layer that includes a target metal line with a target interconnecting via/contact into a first sub-pattern and a second sub-pattern. The target metal line is decomposed into a first line feature pattern that is part of the first sub-pattern and a second line feature pattern that is part of the second sub-pattern such that the first and second line feature patterns have overlapping portions defining a stitch that corresponds to the target interconnecting via/contact. A first photomask is generated that corresponds to the first sub-pattern. A second photomask is generated that corresponds to the second sub-pattern.

Abstract: In one example, a method includes forming a template having a plurality of elements above a process layer and forming spacers on sidewalls of the plurality of elements. Portions of the process layer are exposed between adjacent spacers. At least one of the plurality of elements is removed. A mask structure is formed from a directed self-assembly material over the exposed portions. The process layer is patterned using at least the mask structure as an etch mask.

Abstract: Approaches for multilayer pattern transfer for chemical guides are provided. In a typical embodiment, a device is formed by forming an etch mask layer (e.g., a nitride layer and an oxide layer) over a substrate (e.g., silicon (Si)). An orientation control layer (e.g., a neutral layer) is then formed over the etch mask layer, and an ARC layer (e.g., SiARC) is formed over the orientation control layer. In other embodiments, an organic planarization layer (OPL) and/or a protection layer may also be formed between the ARC layer and the orientation control layer. Regardless, a tapered etch profile/pattern may then be formed through the ARC and/or other layers.

Abstract: Methods for fabricating integrated circuits are provided. One method includes decomposing a master pattern layout for a semiconductor device layer that includes a target metal line with a target interconnecting via/contact into a first sub-pattern and a second sub-pattern. The target metal line is decomposed into a first line feature pattern that is part of the first sub-pattern and a second line feature pattern that is part of the second sub-pattern such that the first and second line feature patterns have overlapping portions defining a stitch that corresponds to the target interconnecting via/contact. A first photomask is generated that corresponds to the first sub-pattern. A second photomask is generated that corresponds to the second sub-pattern.

Abstract: Solid state avalanche photodiode devices and methods of producing the same are described herein.

Abstract: Methods for fabricating guide patterns and methods for fabricating integrated circuits using guide patterns are provided. In an embodiment, a method for fabricating a guide pattern includes forming a coating of a material with latent grafting sites and a photosensitive component configured to activate the latent grafting sites upon exposure over a substrate. The method exposes selected latent grafting sites in the coating to convert the selected latent grafting sites to active grafting sites. A grafting agent is bonded to the active grafting sites to form the guide pattern.

Abstract: The plug comprises a nut, a coupling extending from the nut and adapted to receive an ignition wire and an insulator extending from the nut and away from the coupling. A positive electrode extends through the insulator. An externally-threaded tubular portion extends from the nut in surrounding relation to the insulator and terminating, short of the insulator end, in a cap that is disposed in spaced relation to the insulator. The cap defines a void having: a central portion into which the positive electrode extends; an annular channel surrounding the central portion; and a plurality of lobes, each positioned with respect to the central portion as the planet gears are positioned with respect to the sun gear in a planetary gear. The cap has a central surface that is axially spaced from the insulator and a convex surface that surrounds and extends to the central surface.

Abstract: A method includes forming at least one fin on a semiconductor substrate. A hard mask layer is formed above the fin. A first directed self-assembly material is formed above the hard mask layer. The hard mask layer is patterned using a portion of the first directed self-assembly material as an etch mask to expose a portion of the top surface of the fin. A substantially vertical nanowire is formed on the exposed top surface. At least one dimension of the substantially vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material.

Abstract: A method includes forming at least one fin on a semiconductor substrate. A nanowire material is formed above the fin. A hard mask layer is formed above the fin. A first directed self-assembly material is formed above the hard mask layer. The hard mask layer is patterned using a portion of the first directed self-assembly material as an etch mask to expose a portion of the nanowire material. The nanowire material is etched using the hard mask layer as an etch mask to define a substantially vertical nanowire on a top surface of the at least one fin, wherein at least one dimension of the substantially vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material.

Abstract: A method includes forming a first directed self-assembly material above a substrate. The substrate is patterned using the first directed self-assembly material to define at least one fin in the semiconductor substrate. A second directed self-assembly material is formed above the at least one fin to expose a top surface of the at least one fin. A substantially vertical nanowire is formed on the top surface of the at least one fin. At least a first dimension of the vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material and a second dimension of the vertical nanowire is defined by an intrinsic pitch of the second directed self-assembly material.

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a graphoepitaxy DSA directing confinement well using a sidewall of an etch layer that overlies a semiconductor substrate. The graphoepitaxy DSA directing confinement well is filled with a block copolymer. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etchable phase is etched while leaving the etch resistant phase substantially in place to define an etch mask with a nanopattern. The nanopattern is transferred to the etch layer.

Abstract: Methods for directed self-assembly (DSA) using chemoepitaxy in the design and fabrication of integrated circuits are disclosed herein. An exemplary method includes forming an A or B-block attracting layer over a base semiconductor layer, forming a trench in the A or B-block attracting layer to expose a portion of the base semiconductor layer, and forming a neutral brush or mat or SAMs layer coating within the trench and over the base semiconductor layer. The method further includes forming a block copolymer layer over the neutral layer coating and over the A or B-block attracting layer and annealing the block copolymer layer to form a plurality of vertically-oriented, cylindrical structures within the block copolymer layer.

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a graphoepitaxy DSA directing confinement well using a sidewall of an etch layer that overlies a semiconductor substrate. The graphoepitaxy DSA directing confinement well is filled with a block copolymer. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etchable phase is etched while leaving the etch resistant phase substantially in place to define an etch mask with a nanopattern. The nanopattern is transferred to the etch layer.

Abstract: In one example, a method includes forming a template having a plurality of elements above a process layer and forming spacers on sidewalls of the plurality of elements. Portions of the process layer are exposed between adjacent spacers. At least one of the plurality of elements is removed. A mask structure is formed from a directed self-assembly material over the exposed portions. The process layer is patterned using at least the mask structure as an etch mask.

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes surface treating exposed portions of an anti-reflective coating (ARC) that overlie a semiconductor substrate to form surface treated ARC portions. A neutral layer is formed overlying the anti-reflective coating including over the surface treated ARC portions. First portions of the neutral layer are selectively removed and second portions of the anti-reflective coating that are disposed under the first portions laterally adjacent to the surface treated ARC portions are exposed to define a guide pattern. A block copolymer layer is deposited overlying the guide pattern. The block copolymer layer is phase separated to define a nanopattern that is registered to the guide pattern.

Abstract: The plug comprises a nut, a coupling extending from the nut and adapted to receive an ignition wire and an insulator extending from the nut and away from the coupling. A positive electrode extends through the insulator. An externally-threaded tubular portion extends from the nut in surrounding relation to the insulator and terminating, short of the insulator end, in a cap that is disposed in spaced relation to the insulator. The cap defines a void having: a central portion into which the positive electrode extends; an annular channel surrounding the central portion; and a plurality of lobes, each positioned with respect to the central portion as the planet gears are positioned with respect to the sun gear in a planetary gear. The cap has a central surface that is axially spaced from the insulator and a convex surface that surrounds and extends to the central surface.

Abstract: The plug comprises a nut, a coupling extending from the nut and adapted to receive an ignition wire and an insulator extending from the nut and away from the coupling. A positive electrode extends through the insulator. An externally-threaded tubular portion extends from the nut in surrounding relation to the insulator and terminating, short of the insulator end, in a cap that is disposed in spaced relation to the insulator. The cap defines a void having: a central portion into which the positive electrode extends; an annular channel surrounding the central portion; and a plurality of lobes, each positioned with respect to the central portion as the planet gears are positioned with respect to the sun gear in a planetary gear. The cap has a central surface that is axially spaced from the insulator and a convex surface that surrounds and extends to the central surface.