Abstract: An integrated circuit memory including an array of memory cells divided into several sections, and several rows of column decoding amplifiers, the respective outputs of which are interconnected, by column, by means of a decoded bit line, each decoded bit line including two perpendicular sections, one of which is in the row direction to directly connect each decoded bit line to an input of an input-output stage of the memory arranged at one end of the rows.

Abstract: Each memory cell of a memory device is connected to a bit line of a memory array and is associated with a read/rewrite amplifier connected between the bit line and a reference bit line. The bit line and the reference bit line are precharged to a predetermined precharge voltage. The content of a selected memory cell is read and refreshed based upon an associated read/rewrite amplifier. Between the precharging and the reading and refreshing, two capacitors previously charged to a charging voltage greater than the precharge voltage are respectively connected to the bit line and to the reference bit line.

Abstract: The present invention relates to an integrated circuit including at least one matrix network of identical elements capable of being individually addressed at least in a first direction and including, at least for this first direction, at least one redundancy element, and a circuit that reversibly inhibits the operation of a defective element and maintains the circuit operation by using the redundancy element.

Abstract: A dynamic memory circuit including memory cells arranged in an array of rows and columns, each row capable of being activated by a word line and each column being formed of cells connected to a first and to a second bit lines, which includes at least one, spare row formed of static memory cells, adapted to being activated to replace a memory cell row, each spare cell being connected to the first and second bit lines of a column of the circuit.

Abstract: A voltage regulation device is for a reference cell of a dynamic random access memory arranged in lines and columns and including a plurality of memory cells. The device includes at least one capacitor of a predetermined capacitance which can be discharged during memory access.

Abstract: An electronic circuit with digital output including an auto-stable assembly of latches (1), a control assembly (2), a blowable assembly (3), a logic gate (4) including a first input connected to a common point (14) between the auto-stable assembly (1) and the blowable assembly (3), and a second input connected to the control input (20) of the electronic circuit. A breaker (5) is controlled by the output of the logic gate (4) and arranged between the auto-stable assembly (1) and ground, and an associated process.

Abstract: At a charging phase, a capacitor (PC) is charged through two complementary charging transistors (TR1, TR2) connected in series to a first terminal (T1) of the capacitor (PC). At a voltage multiplication phase, an input voltage (Vdd) is delivered to the second terminal (T2) of the capacitor and an output voltage (Vout), increased with respect to the input voltage, is recovered at the first terminal (T1) of the, capacitor, and the capacitor is discharged during a discharging phase. During three phases, the substrate (BK2) of the charging transistor (TR2) directly connected to the first terminal (T1) of the capacitor is slaved to the source (S2) of this same charging transistor (TR2), while still keeping the source-substrate junction and the drain-substrate junction of this charging transistor (TR2) reverse-biased.

Abstract: The present invention relates to a DRAM circuit including a plurality of memory cells organized in an array, including switches for associating with each end of each column of the array at least two latches controlled independently from each other to store data written into or read from the considered column.

Abstract: A DRAM made in monolithic form, the cells of which each include a MOS transistor and a capacitor, a second electrode of which is common to all cells of a same row and is covered with an insulator, the insulator being coated with independent conductive elements distributed on a same horizontal plane, two neighboring elements being biased to respective high and low levels.

Abstract: A one-time programmable cell including an inverter providing a logic state according to the state of the cell; a fuse coupled between a first supply voltage and the inverter input; and a current source coupled between the fuse and a second supply voltage. The inverter is supplied from the second supply voltage through a first diode-connected transistor and the current source is formed of a second transistor controlled by the inverter output, this second transistor having a threshold voltage greater than that of the first transistor.

Abstract: A memory device includes a defect memory, a test circuit, and a spare memory. The defect memory and the spare memory have as many rows as the array, and each row of the defect memory and the spare memory are selected when the corresponding row of the array is selected. A test circuit locates defective cells of the array and writes addresses in the defect memory to indicate locations of the defective cells. Additionally, a control circuit selects a row of the array based on a selected row address and redirects access to the corresponding row of the spare memory whenever a selected column address corresponds to one of the addresses stored in the defect memory. In one preferred embodiment, each of the rows of the defect memory stores information indicating if there is a defective cell in the corresponding row of the array and the column address of the defective cell. A computer system including such a memory device is also provided.

Abstract: A method is for reading a dynamic memory and a memory implementing the method. The memory includes at least one bit line, one word line, one storage cell accessible by the bit line and the word line, and one reference line, the storage cell enabling the storage of an initial potential representing a logic information. The method includes a step for the precharging of the bit line and the reference line, to carry the potential of these lines to the level of a reference potential that is different from the initial potential stored in the storage cell and a step for the selection of the storage cell to produce a modification of the potential of the bit line and thus create an initial difference between the potentials of the bit line and the reference line. It also includes a step for discharging the bit line and the reference line and a step for the production of an output signal whose state represents values of the discharge currents.

Abstract: The present invention relates to an integrated circuit including at least one matrix network of identical elements capable of being individually addressed at least in a first direction and including, at least for this first direction, at least one redundancy element, and a circuit that reversibly inhibits the operation of a defective element and maintains the circuit operation by using the redundancy element.

Abstract: A memory read circuit includes an input to be connected to a bit line to which there are connected memory cells, and an output to produce an output logic potential. A current source produces a first current and a current-voltage converter produces the output logic potential. This potential represents the value of a second current obtained by the rerouting of a part of the first current towards the bit line when one of the cells is read, so that once the bit line is charged, the value of this second current is determined solely by the state of the selected cell and is independent of the equivalent capacitive load of the bit line.

Abstract: A memory accessible in read mode only comprises storage elements designed to contain a bit that can assume two levels. Each memory cell comprises a transistor. The transistor of the storage element may include an associated circuit portion to prompt a short circuit between the drain and the source of the transistor if the storage element has to contain one bit at one of the two levels. Furthermore, the use of an unbalanced differential amplifier permits an improvement of the access time of the memory.

Abstract: The invention concerns a memory cell insensitive to disturbances. The memory cell, that contains information in the form of two complementary logical levels (X, C(X)), each logical level being stored in a node of the cell (N1, N2), is characterized in that it comprises means of storing the same logical level in two different nodes (N1, N2, N3, N4), the said means being able to restore any logical level to its initial state preceding a modification made on it due to a disturbance, as a result of holding the value of one of the two logical levels complementary to the logical level that was modified.

Abstract: A novel redundancy architecture for an integrated-circuit memory is utilized having no redundancy columns separate from the useful columns but with each useful column, except for the first column, serving as a redundancy column for any adjacent defective column. If a column of order j, normally designated by an output of order j of the column decoder DC, is serviceable, it is actually this column which will be selected by the corresponding output of the decoder DC. On the other hand, if the column is defective, no specialized remote redundancy column will be sought for the repair but instead the output of the decoder will be made to select the following column (order j+1), which would normally have been designated by the following output (order j+1) of the decoder. The other decoder output will be routed towards a third column (order j+2), etc. Therefore, the links between the decoder outputs and the column used will be progressively offset.

Abstract: A frequency divider, constituted by N divide-by-two binaries, comprises logic circuits that enable the generation of a signal of the end of the frequency division by means of the change in state of the most significant bit generated by the Nth order divide-by-two binary. A binary code C representing a decimal integer value V is applied to the divider circuit. The frequency divider comprises circuits that enable the performance of a variable order division (V+1, V, . . . V-p, where p is a whole number greater than or equal to 1 and smaller than N-1) for one and the same binary code C.

Abstract: Disclosed is an integrated circuit memory comprising at least one column of memory cells parallel connected with one another and connected to at least one bit line, each memory cell being connected to a bit line by at least one access transistor, wherein said memory contains a protection transistor that is connected to the bit line and controlled so as to be made conductive so as to limit the voltage drop on the bit line, during the stages of the reading of the memory, when this drop in voltage goes beyond a threshold having a value smaller than a value that prompts the writing of an information element in a memory cell.

Abstract: A self-synchronization device is disclosed for output circuits comprising a "3-state" gate of memories working in internal clock mode. This device consists of a sequential logic circuit which allows the "3-state" gate to go into low impedance only when a datum is available at the output of the read amplifiers.