Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.

Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.

Abstract: An intermediate product for an integrated circuit is disclosed. The intermediate product comprises a first portion of a conductive layer, preferably a layer of noble metal, which will form an upper electrode of a capacitor or a patterned wiring. The intermediate product also comprises an adjacent second portion of the conductive layer, the second portion being a removable silicide of the conductive layer.

Abstract: A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices.

Abstract: A method used to form a semiconductor device provides a silicide layer on a plurality of transistor word lines and on a plurality of conductive plugs. In one embodiment, the word lines, one or more sacrificial dielectric layers on the word lines, conductive plugs, and a conductive enhancement layer are formed through the use of a single mask. An in-process semiconductor device which can be formed using one embodiment of the inventive method is also described.

Abstract: Method and structure use support layers to assist in planarization processes to form conductive materials (e.g., a Group VIII metal) in an opening. Further, such method and structure may use a Group VIII metal as an etch stop or end point for the planarization process with subsequent etching to remove undesired portions of the Group VIII metal. One exemplary method of providing a conductive material in an opening includes providing a substrate assembly having at least one surface and providing an opening defined through the surface of the substrate assembly. The opening is defined by at least one surface. At least one conductive material (e.g., at least one Group VIII metal such platinum and/or rhodium) is formed within the opening on the at least one surface defining the opening and on at least a portion of the substrate assembly surface. A support film (e.g., an oxide material) is formed over the conductive material and a fill material (e.g.

Abstract: The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate comprising a gate oxide layer, a conducting layer, and a first insulating layer. Sidewall spacers are formed adjacent to the sides of the gate stack structure and a third insulating layer is formed over the gate stack and substrate. The third insulating layer and first insulating layer are removed to expose the conducting layer and, at least one unetched metal-containing layer is formed over and in contact with the conducting layer. The gate stack structure then undergoes a siliciding process with different variations to finally form a silicide gate.

Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.

Abstract: In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions.

Abstract: The invention is a method of depositing an aluminum nitride comprising layer over a semiconductor substrate, a method of forming DRAM circuitry, DRAM circuitry, a method of forming a field emission device, and a field emission device. In one aspect, a method of depositing an aluminum nitride comprising layer over a semiconductor substrate includes positioning a semiconductor substrate within a chemical vapor deposition reactor. Ammonia and at least one of triethylaluminum and trimethylaluminum are fed to the reactor while the substrate is at a temperature of about 500° C. or less and at a reactor pressure from about 100 mTorr to about 725 Torr effective to deposit a layer comprising aluminum nitride over the substrate at such temperature and reactor pressure. In one aspect, such layer is utilized as a cell dielectric layer in DRAM circuitry. In one aspect, such layer is deposited over emitters of a field emission display.

Abstract: Method and structure use support layers to assist in, for example, planarization processes to form conductive materials (e.g., a Group VIII metal) in an opening. Further, for example, such method and structure may use a Group VIII metal as an etch stop or end point for the planarization process with subsequent etching to remove undesired portions of the Group VIII metal.

Abstract: DRAM circuitry includes an array of word lines forming gates of field effect transistors and an array of bit lines. Individual field effect transistors include a pair of source/drain regions. A plurality of memory cell storage capacitors are associated with the field effect transistors. Individual storage capacitors include a first capacitor electrode in electrical connection with one of a pair of source/drain regions of one of the field effect transistors and a second capacitor electrode. A capacitor dielectric region is received intermediate the first and second capacitor electrodes. The capacitor dielectric region includes aluminum nitride. The other of the pair of source/drain regions of the one field effect transistor are in electrical connection with one of the bit lines.

Abstract: In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride laver and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions.

Abstract: The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate comprising a gate oxide layer, a conducting layer, and a first insulating layer. Sidewall spacers are formed adjacent to the sides of the gate stack structure and a third insulating layer is formed over the gate stack and substrate. The third insulating layer and first insulating layer are removed to expose the conducting layer and, at least one unetched metal-containing layer is formed over and in contact with the conducting layer. The gate stack structure then undergoes a siliciding process with different variations to finally form a silicide gate.

Abstract: A process and apparatus directed to forming metal plugs in a peripheral logic circuitry area of a semiconductor device to contact both N+ and P+ doped regions of transistors in the peripheral logic circuitry area. The metal plugs are formed after all high temperature processing used in wafer fabrication is completed. The metal plugs are formed without metal diffusing into the active areas of the substrate. The metal plugs may form an oval slot as seen from a top down view of the semiconductor device.

Abstract: A process and apparatus directed to forming metal plugs in a peripheral logic circuitry area of a semiconductor device to contact both N+ and P+ doped regions of transistors in the peripheral logic circuitry area. The metal plugs are formed after all high temperature processing used in wafer fabrication is completed. The metal plugs are formed without metal diffusing into the active areas of the substrate. The metal plugs may form an oval slot as seen from a top down view of the semiconductor device.

Abstract: The invention is a method of depositing an aluminum nitride comprising layer over a semiconductor substrate, a method of forming DRAM circuitry, DRAM circuitry, a method of forming a field emission device, and a field emission device. In one aspect, a method of depositing an aluminum nitride comprising layer over a semiconductor substrate includes positioning a semiconductor substrate within a chemical vapor deposition reactor. Ammonia and at least one of triethylaluminum and trimethylaluminum are fed to the reactor while the substrate is at a temperature of about 500° C. or less and at a reactor pressure from about 100 mTorr to about 725 Torr effective to deposit a layer comprising aluminum nitride over the substrate at such temperature and reactor pressure. In one aspect, such layer is utilized as a cell dielectric layer in DRAM circuitry. In one aspect, such layer is deposited over emitters of a field emission display.

Abstract: A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices.

Abstract: The invention encompasses a method of forming a portion of a transistor structure. A substrate is provided, and a transistor gate is formed over the substrate. The transistor gate has a sidewall. A silicon oxide is deposited over a portion of the substrate proximate the transistor gate by high density plasma deposition. A spacer is formed over the silicon oxide and along the sidewall of the transistor gate. The invention also encompasses a method of oxidizing a portion of a conductive structure. Additionally, the invention encompasses transistor gate structures, as well as structures comprising memory array and peripheral circuitry.

Abstract: This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduces the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.

Abstract: The present invention relates to compounds of formula I ##STR1## or a salt, ester or amide thereof; wherein R.sup.1 is --CH.sub.2 --CH.sub.2 --, CH.sub.2 --O-- or --O--CH.sub.2 --; R.sup.2 and R.sup.3 are the same or different and are each hydrogen, C.sub.1-4 alkyl or taken together with the nitrogen comprise a nitrogen-containing heterocyclic ring having four to six ring members; R.sup.4 is a single bond or a C.sub.1-7 bivalent aliphatic hydrocarbon group and may be joined to the aromatic ring system at the 2,3,8 or 9 positions; n is 0 to 3, and their use as antihistamine and antiasthma agents.