Patents by Inventor Richard Ho

Richard Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240076123
    Abstract: A sanitary product disposal container includes a container housing having a movable housing top cover. A cover hinge assembly allows the top cover to pivot between open and closed positions. Accordingly, a used feminine hygiene product may be placed in the interior space of the container housing in the open position of the housing top cover while minimizing touching the container housing to open the housing top cover. The housing may be selectively opened to facilitate removal of the used feminine hygiene products from the interior space all without exposure to the used products or the escape of unpleasant odors.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 7, 2024
    Inventors: Richard R. Bing, Megan Kathryn Helms, David Steven Mesko, Emily Yeager, Pil Ho Chung, Joshua Meador, Marco Perry, Brooke Williams
  • Patent number: 11919869
    Abstract: Provided herein is A compound of Formula I: or a pharmaceutically acceptable salt thereof, wherein the various substituents are described herein.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: March 5, 2024
    Assignee: Gilead Sciences, Inc.
    Inventors: Mark J. Bartlett, Gregory F. Chin, Michael O. Clarke, Jennifer L Cosman, Deeba Ensan, Bindu Goyal, Stephen Ho, Richard L Mackman, Michael R. Mish, Dustin S. Siegel, Kyle C. Tamshen, Hai Yang
  • Patent number: 11853677
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: December 26, 2023
    Assignee: Google LLC
    Inventors: Anna Darling Goldie, Azalia Mirhoseini, Ebrahim Songhori, Wenjie Jiang, Shen Wang, Roger David Carpenter, Young-Joon Lee, Mustafa Nazim Yazgan, Chian-min Richard Ho, Quoc V. Le, James Laudon, Jeffrey Adgate Dean, Kavya Srinivasa Setty, Omkar Pathak
  • Publication number: 20230394203
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.
    Type: Application
    Filed: May 1, 2023
    Publication date: December 7, 2023
    Inventors: Chian-min Richard Ho, William Hang, Mustafa Nazim Yazgan, Anna Darling Goldie, Jeffrey Adgate Dean, Azalia Mirhoseini, Emre Tuncer, Ya Wang, Anand Babu
  • Publication number: 20230376645
    Abstract: This document discloses systems and methods for implementing automatic test parameter tuning in constrained random verification. In aspects, a method receives a first set of parameters for testing a design under test, performs a first regression (e.g., an overnight regression test) on a design under test using the first set of parameters, and analyzes the results of the first regression including determining a coverage percentage. The method then generates an optimized set of parameters based on the analysis of the results of the first regression and performs an additional regression on the design under test using the optimized set of parameters. In aspects, the method is repeated using the optimized set of parameters until a coverage percentage is reached, or in some implementations, full coverage may be reached. Some implementations of the method utilize black-box optimization through use of a Bayesian optimization algorithm.
    Type: Application
    Filed: November 5, 2021
    Publication date: November 23, 2023
    Applicant: Google LLC
    Inventors: Hamid Shojaei, Qijing Huang, Chian-min Richard Ho, Satrajit Chatterjee, Shobha Vasudevan, Azade Nazi, Frederick Dennis Zyda
  • Patent number: 11735413
    Abstract: A method for depositing a silicon-containing film, the method comprising: placing a substrate comprising at least one surface feature into a flowable CVD reactor; introducing into the reactor at least one silicon-containing compound and at least one multifunctional organoamine compound to at least partially react the at least one silicon-containing compound to form a flowable liquid oligomer wherein the flowable liquid oligomer forms a silicon oxide coating on the substrate and at least partially fills at least a portion of the at least one surface feature. Once cured, the silicon carbonitride coating has excellent mechanical properties.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: August 22, 2023
    Assignee: Versum Materials US, LLC
    Inventors: Manchao Xiao, Daniel P. Spence, Richard Ho
  • Patent number: 11675940
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: June 13, 2023
    Assignee: Google LLC
    Inventors: Chian-Min Richard Ho, William Hang, Mustafa Nazim Yazgan, Anna Darling Goldie, Jeffrey Adgate Dean, Azalia Mirhoseini, Emre Tuncer, Ya Wang, Anand Babu
  • Publication number: 20230117786
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.
    Type: Application
    Filed: December 15, 2022
    Publication date: April 20, 2023
    Inventors: Anna Darling Goldie, Azalia Mirhoseini, Ebrahim Songhori, Wenjie Jiang, Shen Wang, Roger David Carpenter, Young-Joon Lee, Mustafa Nazim Yazgan, Chian-min Richard Ho, Quoc V. Le, James Laudon, Jeffrey Adgate Dean, Kavya Srinivasa Setty, Omkar Pathak
  • Patent number: 11584854
    Abstract: Described herein are compositions and methods for forming silicon oxide films. In one aspect, the film is deposited from at least one silicon precursor compound, wherein the at least one silicon precursor compound is selected from the following Formulae A and B: as defined herein.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: February 21, 2023
    Assignee: Versum Materials US, LLC
    Inventors: Xinjian Lei, Meiliang Wang, Matthew R. MacDonald, Richard Ho, Manchao Xiao, Suresh Kalpatu Rajaraman
  • Patent number: 11556690
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: January 17, 2023
    Assignee: Google LLC
    Inventors: Anna Darling Goldie, Azalia Mirhoseini, Ebrahim Songhori, Wenjie Jiang, Shen Wang, Roger David Carpenter, Young-Joon Lee, Mustafa Nazim Yazgan, Chian-min Richard Ho, Quoc V. Le, James Laudon, Jeffrey Adgate Dean, Kavya Srinivasa Setty, Omkar Pathak
  • Publication number: 20220234903
    Abstract: A composition comprises at least one a composition comprising at least one organosilicon compound which has two or more silicon atoms connected to either a carbon atom or a hydrocarbon moiety.
    Type: Application
    Filed: May 21, 2020
    Publication date: July 28, 2022
    Applicant: VERSUM MATERIALS US, LLC
    Inventors: RONALD M. PEARLSTEIN, MANCHAO XIAO, RICHARD HO, XINJIAN LEI
  • Publication number: 20220108058
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.
    Type: Application
    Filed: December 17, 2021
    Publication date: April 7, 2022
    Inventors: Anna Darling Goldie, Azalia Mirhoseini, Ebrahim Songhori, Wenjie Jiang, Shen Wang, Roger David Carpenter, Young-Joon Lee, Mustafa Nazim Yazgan, Chian-min Richard Ho, Quoc V. Le, James Laudon, Jeffrey Adgate Dean, Kavya Srinivasa Setty, Omkar Pathak
  • Publication number: 20220043951
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.
    Type: Application
    Filed: August 23, 2021
    Publication date: February 10, 2022
    Inventors: Chian-min Richard Ho, William Hang, Mustafa Nazim Yazgan, Anna Darling Goldie, Jeffrey Adgate Dean, Azalia Mirhoseini, Emre Tuncer, Ya Wang, Anand Babu
  • Patent number: 11216609
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: January 4, 2022
    Assignee: Google LLC
    Inventors: Anna Darling Goldie, Azalia Mirhoseini, Ebrahim Songhori, Wenjie Jiang, Shen Wang, Roger David Carpenter, Young-Joon Lee, Mustafa Nazim Yazgan, Chian-Min Richard Ho, Quoc V. Le, James Laudon, Jeffrey Adgate Dean, Kavya Srinivasa Setty, Omkar Pathak
  • Publication number: 20210407793
    Abstract: Described herein are precursors and methods for forming silicon-containing films. In one aspect, the precursor comprises a compound represented by one of following Formulae A through E below: In one particular embodiment, the organoaminosilane precursors are effective for a low temperature (e.g., 350° C. or less), atomic layer deposition (ALD) or plasma enhanced atomic layer deposition (PEALD) of a silicon-containing film. In addition, described herein is a composition comprising an organoaminosilane described herein wherein the organoaminosilane is substantially free of at least one selected from the amines, halides (e.g., Cl, F, I, Br), higher molecular weight species, and trace metals.
    Type: Application
    Filed: September 8, 2021
    Publication date: December 30, 2021
    Applicant: VERSUM MATERIALS US, LLC
    Inventors: MARK LEONARD O'NEILL, MANCHAO XIAO, XINJIAN LEI, RICHARD HO, HARIPIN CHANDRA, MATTHEW R. MACDONALD, MEILIANG WANG
  • Patent number: D1016783
    Type: Grant
    Filed: May 10, 2023
    Date of Patent: March 5, 2024
    Assignee: Apple Inc.
    Inventors: Jody Akana, Molly Anderson, Bartley K. Andre, Shota Aoyagi, Anthony Michael Ashcroft, Marine C. Bataille, Jeremy Bataillou, Abidur Rahman Chowdhury, Clara Geneviève Marine Courtaigne, Markus Diebel, Jonathan Gomez Garcia, M. Evans Hankey, Richard P. Howarth, Jonathan P. Ive, Julian Jaede, Duncan Robert Kerr, Peter Russell-Clarke, Benjamin Andrew Shaffer, Sung-Ho Tan, Clement Tissandier, Eugene Antony Whang
  • Patent number: D1018548
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: March 19, 2024
    Assignee: Apple Inc.
    Inventors: Jody Akana, Molly Anderson, Bartley K. Andre, Shota Aoyagi, Anthony Michael Ashcroft, Marine C. Bataille, Jeremy Bataillou, Adam T. Clavelle, Erik Geddes Pieter De Jong, Markus Diebel, M. Evans Hankey, Julian Hoenig, Richard P. Howarth, Jonathan P. Ive, Julian Jaede, Duncan Robert Kerr, Martin Melcher, Peter Russell-Clarke, Benjamin Andrew Shaffer, Mikael Silvanto, Sung-Ho Tan, Clement Tissandier, Eugene Antony Whang, Rico Zörkendörfer
  • Patent number: D1018549
    Type: Grant
    Filed: July 13, 2023
    Date of Patent: March 19, 2024
    Assignee: Apple Inc.
    Inventors: Jody Akana, Molly Anderson, Bartley K. Andre, Shota Aoyagi, Anthony Michael Ashcroft, Marine C. Bataille, Jeremy Bataillou, Markus Diebel, M. Evans Hankey, Julian Hoenig, Richard P. Howarth, Jonathan P. Ive, Julian Jaede, Duncan Robert Kerr, Peter Russell-Clarke, Benjamin Andrew Shaffer, Mikael Silvanto, Sung-Ho Tan, Clement Tissandier, Eugene Antony Whang, Rico Zörkendörfer
  • Patent number: D1023009
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: April 16, 2024
    Assignee: Apple Inc.
    Inventors: Jody Akana, Molly Anderson, Bartley K. Andre, Shota Aoyagi, Anthony Michael Ashcroft, John J. Baker, Marine C. Bataille, Jeremy Bataillou, Abidur Rahman Chowdhury, Clara Geneviève Marine Courtaigne, Markus Diebel, Richard Hung Minh Dinh, Christopher E. Glazowski, Jonathan Gomez Garcia, Jean-Pierre S. Guillou, M. Evans Hankey, Matthew David Hill, Julian Hoenig, Richard P. Howarth, Jonathan P. Ive, Julian Jaede, Duncan Robert Kerr, Peter Russell-Clarke, Benjamin Andrew Shaffer, Sung-Ho Tan, Clement Tissandier, Eugene Antony Whang, Rico Zörkendörfer
  • Patent number: D1025075
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: April 30, 2024
    Assignee: Apple Inc.
    Inventors: Jody Akana, Molly Anderson, Bartley K. Andre, Shota Aoyagi, Anthony Michael Ashcroft, Marine C. Bataille, Jeremy Bataillou, Eric Wesley Bates, Mu-Hua Cheng, Sawyer Isaac Cohen, Markus Diebel, Richard Hung Minh Dinh, M. Evans Hankey, Julian Hoenig, Richard P. Howarth, Jonathan P. Ive, Julian Jaede, Hugh J. Jay, Duncan Robert Kerr, Peter Russell-Clarke, Benjamin Andrew Shaffer, Mikael Silvanto, Sung-Ho Tan, Clement Tissandier, Eugene Antony Whang, Rico Zörkendörfer