Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.

Abstract: Described herein are precursors and methods for forming silicon-containing films. In one aspect, the precursor comprises a compound represented by one of following Formulae A through E below: In one particular embodiment, the organoaminosilane precursors are effective for a low temperature (e.g., 350° C. or less), atomic layer deposition (ALD) or plasma enhanced atomic layer deposition (PEALD) of a silicon-containing film. In addition, described herein is a composition comprising an organoaminosilane described herein wherein the organoaminosilane is substantially free of at least one selected from the amines, halides (e.g., Cl, F, I, Br), higher molecular weight species, and trace metals.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.

Abstract: Described herein is a packaging approach that employs a remapping layer to maintain compatibility to different types of electronic chips while allowing chip designers to standardize the layout of the electrical interface of a photonic interposer. A remapping layer remaps the electrical interface of an electronic chip to the electrical interface of a photonic interposer. Remapping layers may be implemented in various ways, including for example as monolithic electronic interposers and/or as individual remapping chips. In some embodiments, to reduce manufacturing costs, remapping layers may be implemented using passive electronics (without transistors). Because remapping layers are significantly less costly to manufacture than photonic interposers, shifting the need to provide ad hoc electrical interfaces from the photonic interposer to the remapping layer enhances the applicability of photonic interposers in computational, telecom and datacom settings.

Abstract: Described herein are compositions and methods using same for forming a silicon-containing film such as without limitation a silicon oxide, silicon nitride, silicon oxynitride, a carbon-doped silicon nitride, or a carbon-doped silicon oxide film on at least a surface of a substrate having a surface feature. In one aspect, the silicon-containing films are deposited using a compound having Formula I or II described herein.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating learned representations of digital circuit designs. One of the systems includes obtaining data representing a program that implements a digital circuit design, the program comprising a plurality of statements; processing the obtained data to generate data representing a graph representing the digital circuit design, the graph comprising: a plurality of nodes representing respective statements of the program, a plurality of first edges each representing a control flow between a pair of statements of the program, and a plurality of second edges each representing a data flow between a pair of statements of the program; and generating a learned representation of the digital circuit design, comprising processing the data representing the graph using a graph neural network to generate a respective learned representation of each statement represented by a node of the graph.

Abstract: Provided herein are optical fiber arrays and optical assemblies included optical fiber arrays. The optical fiber array includes a fiber array chip that has first optical connections disposed on a first edge of the fiber array chip and second optical connections disposed on a second edge of the fiber array chip. Optical fibers are coupled to the first optical connections. Active devices (e.g., photonic and/or electronic devices) are disposed on the fiber array chip. The optical fiber array is removably, optically couplable to another optical component such as a photonic integrated circuit.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.

Abstract: Described herein are techniques for intra-chip communication within tiled photonic interposers. A photonic interposer may rely on a combination of photonic lanes and electric lanes. For example, a photonic interposer may comprise a photonic integrated circuit (PIC) lithographically patterned with an array of photonic tiles, each photonic tile comprising an on-chip communication unit. The array of photonic tiles is arranged in rows and columns. A plurality of electric lanes place the on-chip communication units of photonic tiles of different rows in electrical communication with one another. A plurality of photonic lanes place the on-chip communication units of photonic tiles of different columns in optical communication with one another.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.

Abstract: This document discloses systems and methods for implementing automatic test parameter tuning in constrained random verification. In aspects, a method receives a first set of parameters for testing a design under test, performs a first regression (e.g., an overnight regression test) on a design under test using the first set of parameters, and analyzes the results of the first regression including determining a coverage percentage. The method then generates an optimized set of parameters based on the analysis of the results of the first regression and performs an additional regression on the design under test using the optimized set of parameters. In aspects, the method is repeated using the optimized set of parameters until a coverage percentage is reached, or in some implementations, full coverage may be reached. Some implementations of the method utilize black-box optimization through use of a Bayesian optimization algorithm.

Abstract: A method for depositing a silicon-containing film, the method comprising: placing a substrate comprising at least one surface feature into a flowable CVD reactor; introducing into the reactor at least one silicon-containing compound and at least one multifunctional organoamine compound to at least partially react the at least one silicon-containing compound to form a flowable liquid oligomer wherein the flowable liquid oligomer forms a silicon oxide coating on the substrate and at least partially fills at least a portion of the at least one surface feature. Once cured, the silicon carbonitride coating has excellent mechanical properties.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.

Abstract: Described herein are compositions and methods for forming silicon oxide films. In one aspect, the film is deposited from at least one silicon precursor compound, wherein the at least one silicon precursor compound is selected from the following Formulae A and B: as defined herein.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.

Abstract: A composition comprises at least one a composition comprising at least one organosilicon compound which has two or more silicon atoms connected to either a carbon atom or a hydrocarbon moiety.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.