Patents by Inventor Richard Ho
Richard Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240076123Abstract: A sanitary product disposal container includes a container housing having a movable housing top cover. A cover hinge assembly allows the top cover to pivot between open and closed positions. Accordingly, a used feminine hygiene product may be placed in the interior space of the container housing in the open position of the housing top cover while minimizing touching the container housing to open the housing top cover. The housing may be selectively opened to facilitate removal of the used feminine hygiene products from the interior space all without exposure to the used products or the escape of unpleasant odors.Type: ApplicationFiled: September 5, 2023Publication date: March 7, 2024Inventors: Richard R. Bing, Megan Kathryn Helms, David Steven Mesko, Emily Yeager, Pil Ho Chung, Joshua Meador, Marco Perry, Brooke Williams
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Patent number: 11919869Abstract: Provided herein is A compound of Formula I: or a pharmaceutically acceptable salt thereof, wherein the various substituents are described herein.Type: GrantFiled: October 27, 2022Date of Patent: March 5, 2024Assignee: Gilead Sciences, Inc.Inventors: Mark J. Bartlett, Gregory F. Chin, Michael O. Clarke, Jennifer L Cosman, Deeba Ensan, Bindu Goyal, Stephen Ho, Richard L Mackman, Michael R. Mish, Dustin S. Siegel, Kyle C. Tamshen, Hai Yang
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Patent number: 11853677Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.Type: GrantFiled: December 15, 2022Date of Patent: December 26, 2023Assignee: Google LLCInventors: Anna Darling Goldie, Azalia Mirhoseini, Ebrahim Songhori, Wenjie Jiang, Shen Wang, Roger David Carpenter, Young-Joon Lee, Mustafa Nazim Yazgan, Chian-min Richard Ho, Quoc V. Le, James Laudon, Jeffrey Adgate Dean, Kavya Srinivasa Setty, Omkar Pathak
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Publication number: 20230394203Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.Type: ApplicationFiled: May 1, 2023Publication date: December 7, 2023Inventors: Chian-min Richard Ho, William Hang, Mustafa Nazim Yazgan, Anna Darling Goldie, Jeffrey Adgate Dean, Azalia Mirhoseini, Emre Tuncer, Ya Wang, Anand Babu
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Publication number: 20230376645Abstract: This document discloses systems and methods for implementing automatic test parameter tuning in constrained random verification. In aspects, a method receives a first set of parameters for testing a design under test, performs a first regression (e.g., an overnight regression test) on a design under test using the first set of parameters, and analyzes the results of the first regression including determining a coverage percentage. The method then generates an optimized set of parameters based on the analysis of the results of the first regression and performs an additional regression on the design under test using the optimized set of parameters. In aspects, the method is repeated using the optimized set of parameters until a coverage percentage is reached, or in some implementations, full coverage may be reached. Some implementations of the method utilize black-box optimization through use of a Bayesian optimization algorithm.Type: ApplicationFiled: November 5, 2021Publication date: November 23, 2023Applicant: Google LLCInventors: Hamid Shojaei, Qijing Huang, Chian-min Richard Ho, Satrajit Chatterjee, Shobha Vasudevan, Azade Nazi, Frederick Dennis Zyda
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Patent number: 11735413Abstract: A method for depositing a silicon-containing film, the method comprising: placing a substrate comprising at least one surface feature into a flowable CVD reactor; introducing into the reactor at least one silicon-containing compound and at least one multifunctional organoamine compound to at least partially react the at least one silicon-containing compound to form a flowable liquid oligomer wherein the flowable liquid oligomer forms a silicon oxide coating on the substrate and at least partially fills at least a portion of the at least one surface feature. Once cured, the silicon carbonitride coating has excellent mechanical properties.Type: GrantFiled: October 20, 2017Date of Patent: August 22, 2023Assignee: Versum Materials US, LLCInventors: Manchao Xiao, Daniel P. Spence, Richard Ho
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Patent number: 11675940Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.Type: GrantFiled: August 23, 2021Date of Patent: June 13, 2023Assignee: Google LLCInventors: Chian-Min Richard Ho, William Hang, Mustafa Nazim Yazgan, Anna Darling Goldie, Jeffrey Adgate Dean, Azalia Mirhoseini, Emre Tuncer, Ya Wang, Anand Babu
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Publication number: 20230117786Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.Type: ApplicationFiled: December 15, 2022Publication date: April 20, 2023Inventors: Anna Darling Goldie, Azalia Mirhoseini, Ebrahim Songhori, Wenjie Jiang, Shen Wang, Roger David Carpenter, Young-Joon Lee, Mustafa Nazim Yazgan, Chian-min Richard Ho, Quoc V. Le, James Laudon, Jeffrey Adgate Dean, Kavya Srinivasa Setty, Omkar Pathak
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Patent number: 11584854Abstract: Described herein are compositions and methods for forming silicon oxide films. In one aspect, the film is deposited from at least one silicon precursor compound, wherein the at least one silicon precursor compound is selected from the following Formulae A and B: as defined herein.Type: GrantFiled: June 15, 2020Date of Patent: February 21, 2023Assignee: Versum Materials US, LLCInventors: Xinjian Lei, Meiliang Wang, Matthew R. MacDonald, Richard Ho, Manchao Xiao, Suresh Kalpatu Rajaraman
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Patent number: 11556690Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.Type: GrantFiled: December 17, 2021Date of Patent: January 17, 2023Assignee: Google LLCInventors: Anna Darling Goldie, Azalia Mirhoseini, Ebrahim Songhori, Wenjie Jiang, Shen Wang, Roger David Carpenter, Young-Joon Lee, Mustafa Nazim Yazgan, Chian-min Richard Ho, Quoc V. Le, James Laudon, Jeffrey Adgate Dean, Kavya Srinivasa Setty, Omkar Pathak
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Publication number: 20220234903Abstract: A composition comprises at least one a composition comprising at least one organosilicon compound which has two or more silicon atoms connected to either a carbon atom or a hydrocarbon moiety.Type: ApplicationFiled: May 21, 2020Publication date: July 28, 2022Applicant: VERSUM MATERIALS US, LLCInventors: RONALD M. PEARLSTEIN, MANCHAO XIAO, RICHARD HO, XINJIAN LEI
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Publication number: 20220108058Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.Type: ApplicationFiled: December 17, 2021Publication date: April 7, 2022Inventors: Anna Darling Goldie, Azalia Mirhoseini, Ebrahim Songhori, Wenjie Jiang, Shen Wang, Roger David Carpenter, Young-Joon Lee, Mustafa Nazim Yazgan, Chian-min Richard Ho, Quoc V. Le, James Laudon, Jeffrey Adgate Dean, Kavya Srinivasa Setty, Omkar Pathak
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Publication number: 20220043951Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.Type: ApplicationFiled: August 23, 2021Publication date: February 10, 2022Inventors: Chian-min Richard Ho, William Hang, Mustafa Nazim Yazgan, Anna Darling Goldie, Jeffrey Adgate Dean, Azalia Mirhoseini, Emre Tuncer, Ya Wang, Anand Babu
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Patent number: 11216609Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.Type: GrantFiled: April 22, 2021Date of Patent: January 4, 2022Assignee: Google LLCInventors: Anna Darling Goldie, Azalia Mirhoseini, Ebrahim Songhori, Wenjie Jiang, Shen Wang, Roger David Carpenter, Young-Joon Lee, Mustafa Nazim Yazgan, Chian-Min Richard Ho, Quoc V. Le, James Laudon, Jeffrey Adgate Dean, Kavya Srinivasa Setty, Omkar Pathak
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Publication number: 20210407793Abstract: Described herein are precursors and methods for forming silicon-containing films. In one aspect, the precursor comprises a compound represented by one of following Formulae A through E below: In one particular embodiment, the organoaminosilane precursors are effective for a low temperature (e.g., 350° C. or less), atomic layer deposition (ALD) or plasma enhanced atomic layer deposition (PEALD) of a silicon-containing film. In addition, described herein is a composition comprising an organoaminosilane described herein wherein the organoaminosilane is substantially free of at least one selected from the amines, halides (e.g., Cl, F, I, Br), higher molecular weight species, and trace metals.Type: ApplicationFiled: September 8, 2021Publication date: December 30, 2021Applicant: VERSUM MATERIALS US, LLCInventors: MARK LEONARD O'NEILL, MANCHAO XIAO, XINJIAN LEI, RICHARD HO, HARIPIN CHANDRA, MATTHEW R. MACDONALD, MEILIANG WANG
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Patent number: D1016783Type: GrantFiled: May 10, 2023Date of Patent: March 5, 2024Assignee: Apple Inc.Inventors: Jody Akana, Molly Anderson, Bartley K. Andre, Shota Aoyagi, Anthony Michael Ashcroft, Marine C. Bataille, Jeremy Bataillou, Abidur Rahman Chowdhury, Clara Geneviève Marine Courtaigne, Markus Diebel, Jonathan Gomez Garcia, M. Evans Hankey, Richard P. Howarth, Jonathan P. Ive, Julian Jaede, Duncan Robert Kerr, Peter Russell-Clarke, Benjamin Andrew Shaffer, Sung-Ho Tan, Clement Tissandier, Eugene Antony Whang
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Patent number: D1018548Type: GrantFiled: November 28, 2022Date of Patent: March 19, 2024Assignee: Apple Inc.Inventors: Jody Akana, Molly Anderson, Bartley K. Andre, Shota Aoyagi, Anthony Michael Ashcroft, Marine C. Bataille, Jeremy Bataillou, Adam T. Clavelle, Erik Geddes Pieter De Jong, Markus Diebel, M. Evans Hankey, Julian Hoenig, Richard P. Howarth, Jonathan P. Ive, Julian Jaede, Duncan Robert Kerr, Martin Melcher, Peter Russell-Clarke, Benjamin Andrew Shaffer, Mikael Silvanto, Sung-Ho Tan, Clement Tissandier, Eugene Antony Whang, Rico Zörkendörfer
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Patent number: D1018549Type: GrantFiled: July 13, 2023Date of Patent: March 19, 2024Assignee: Apple Inc.Inventors: Jody Akana, Molly Anderson, Bartley K. Andre, Shota Aoyagi, Anthony Michael Ashcroft, Marine C. Bataille, Jeremy Bataillou, Markus Diebel, M. Evans Hankey, Julian Hoenig, Richard P. Howarth, Jonathan P. Ive, Julian Jaede, Duncan Robert Kerr, Peter Russell-Clarke, Benjamin Andrew Shaffer, Mikael Silvanto, Sung-Ho Tan, Clement Tissandier, Eugene Antony Whang, Rico Zörkendörfer
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Patent number: D1023009Type: GrantFiled: May 10, 2022Date of Patent: April 16, 2024Assignee: Apple Inc.Inventors: Jody Akana, Molly Anderson, Bartley K. Andre, Shota Aoyagi, Anthony Michael Ashcroft, John J. Baker, Marine C. Bataille, Jeremy Bataillou, Abidur Rahman Chowdhury, Clara Geneviève Marine Courtaigne, Markus Diebel, Richard Hung Minh Dinh, Christopher E. Glazowski, Jonathan Gomez Garcia, Jean-Pierre S. Guillou, M. Evans Hankey, Matthew David Hill, Julian Hoenig, Richard P. Howarth, Jonathan P. Ive, Julian Jaede, Duncan Robert Kerr, Peter Russell-Clarke, Benjamin Andrew Shaffer, Sung-Ho Tan, Clement Tissandier, Eugene Antony Whang, Rico Zörkendörfer
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Patent number: D1025075Type: GrantFiled: July 11, 2022Date of Patent: April 30, 2024Assignee: Apple Inc.Inventors: Jody Akana, Molly Anderson, Bartley K. Andre, Shota Aoyagi, Anthony Michael Ashcroft, Marine C. Bataille, Jeremy Bataillou, Eric Wesley Bates, Mu-Hua Cheng, Sawyer Isaac Cohen, Markus Diebel, Richard Hung Minh Dinh, M. Evans Hankey, Julian Hoenig, Richard P. Howarth, Jonathan P. Ive, Julian Jaede, Hugh J. Jay, Duncan Robert Kerr, Peter Russell-Clarke, Benjamin Andrew Shaffer, Mikael Silvanto, Sung-Ho Tan, Clement Tissandier, Eugene Antony Whang, Rico Zörkendörfer