Patents by Inventor Richard K. Williams

Richard K. Williams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Isolated trench MOSFET in epi-less semiconductor sustrate
    Patent number: 7737526
    Abstract: An isolation structure for a semiconductor device comprises a floor isolation region, a dielectric filled trench above the floor isolation region and a sidewall isolation region extending downward from the bottom of the trench to the floor isolation region. This structure provides a relatively deep isolated pocket in a semiconductor substrate while limiting the depth of the trench that must be etched in the substrate. A MOSFET is formed in the isolated pocket.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: June 15, 2010
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
  • ESD protection for bipolar-CMOS-DMOS integrated circuit devices
    Patent number: 7738224
    Abstract: An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: June 15, 2010
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Donald Ray Disney, Jun-Wei Chen, Richard K. Williams, HyungSik Ryu, Wai Tien Chan
  • Isolated transistor
    Publication number: 20100133611
    Abstract: A transistor is formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench.
    Type: Application
    Filed: February 1, 2010
    Publication date: June 3, 2010
    Applicant: Advanced Analogic Technologies, Inc.
    Inventors: Donald R. Disney, Richard K. Williams
  • High-voltage lateral DMOS device
    Patent number: 7719054
    Abstract: All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: May 18, 2010
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Donald Ray Disney, Jun-Wei Chen, Wai Tien Chan, HyungSik Ryu
  • Isolation structures for integrated circuits
    Patent number: 7701033
    Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: April 20, 2010
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
  • Heat shrinkable film with (meth)acrylate resin curable adhesive
    Patent number: 7700189
    Abstract: A heat shrinkable label comprises (A) a heat shrinkable film comprising at least one thermoplastic polymer, and (B) a curable adhesive comprising (1) at least one urethane (meth)acrylate resin having an average of about 1 to about 1.6 (meth)acrylate groups per resin molecule, (2) at least one tackifier, and (3) at least one photoinitiator, where the film has an ultimate shrinkage at 135° C. of at least 15%, and the adhesive has sufficient precure tack, wherein the loop tack of the uncured adhesive is at least 4.3 g/cm2. The heat shrinkable label is useful in high-speed industrial processes such as beverage container labeling.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: April 20, 2010
    Assignee: Avery Dennison Corporation
    Inventors: Moris Amon, Christopher J. Blackwell, Farid F. Ghiam, Patricia Ann Harman, Payal Kaul, Sunder R. Rajan, Richard K. Williams, Jr.
  • Edge termination region for high-voltage bipolar-CMOS-DMOS integrated circuit devices
    Patent number: 7683453
    Abstract: All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: March 23, 2010
    Assignee: Advanced Analogic Technologies, Inc.
    Inventors: Richard K. Williams, Donald Ray Disney
  • High-voltage lateral DMOS device with diode clamp
    Patent number: 7683426
    Abstract: All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: March 23, 2010
    Assignee: Advanced Analogic Technologies, Inc.
    Inventors: Richard K. Williams, Donald Ray Disney
  • Method of forming isolation structure for semiconductor integrated circuit substrate
    Publication number: 20100055864
    Abstract: Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths.
    Type: Application
    Filed: April 30, 2008
    Publication date: March 4, 2010
    Applicant: Advanced Analogic Technologies, Inc.
    Inventor: Richard K. Williams
  • Isolated transistor
    Patent number: 7667268
    Abstract: Various integrated circuit devices, in particular a transistor, are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described.
    Type: Grant
    Filed: February 27, 2008
    Date of Patent: February 23, 2010
    Assignee: Advanced Analogic Technologies, Inc.
    Inventors: Donald R. Disney, Richard K. Williams
  • Space-efficient package for laterally conducting device
    Patent number: 7667309
    Abstract: Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: February 23, 2010
    Assignee: GEM Services, Inc.
    Inventors: James Harnden, Allen K. Lam, Richard K. Williams, Anthony Chia, Chu Weibing
  • Methods of fabricating isolation structures in epi-less substrate
    Patent number: 7666756
    Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.
    Type: Grant
    Filed: August 14, 2004
    Date of Patent: February 23, 2010
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
  • Programmable Step-Down Switching Voltage Regulators with Adaptive Power MOSFETs
    Publication number: 20100001704
    Abstract: A step-down switching voltage regulator includes M high-side switches connected between an input voltage and a node; N synchronous rectifiers connected between the node Vx and a ground voltage and an inductor connected between an input voltage and a node Vx and an inductor connected between the node Vx and an output node. An interface circuit decodes a control signal to identify: 1) a subset (m) of the high-side switches, 2) a subset (n) of the synchronous rectifiers. A control circuit drives the high-side switches and synchronous rectifiers in a repeating sequence that includes an inductor charging phase where the high-side switches in the subset m are activated to connect the node Vx to the input voltage; and an inductor discharging phase where the synchronous rectifiers in the subset n are activated to connect the node Vx to the ground voltage.
    Type: Application
    Filed: July 7, 2008
    Publication date: January 7, 2010
    Applicant: ADVANCED ANALOGIC TECHNOLOGIES, INC.
    Inventor: Richard K. Williams
  • Programmable Step-Up Switching Voltage Regulators with Adaptive Power MOSFETs
    Publication number: 20100001703
    Abstract: A step-up switching voltage regulator includes an inductor connected between an input voltage and a node Vx, M low-side switches connected between the node Vx and a ground voltage and N synchronous rectifiers connected between the node Vx and an output node. An interface circuit that decodes a control signal to identify: 1) a subset (m) of the low-side switches, 2) a subset (n) of the synchronous rectifiers, and 3) a reference voltage Vref. A control circuit drives the synchronous rectifiers and low-side switches in a repeating sequence that includes an inductor charging phase where the low-side switches in the subset m are activated to connect the node Vx to the ground voltage; and an inductor discharging phase where the synchronous rectifiers in the subset n are activated to connect the node Vx to the output node.
    Type: Application
    Filed: July 7, 2008
    Publication date: January 7, 2010
    Applicant: ADVANCED ANALOGIC TECHNOLOGIES, INC.
    Inventor: Richard K. Williams
  • Multiple-Output Dual-Polarity DC/DC Converters and Voltage Regulators
    Publication number: 20100002473
    Abstract: A multi-output dual polarity inductive boost converter includes an inductor, a first output node, a second output node, and a switching network, the switching network configured to provide the following modes of circuit operation: a first mode where the positive electrode of the inductor is connected to an input voltage and the negative electrode of the inductor is connected to ground; 2) a second mode the negative electrode of the inductor is connected to ground and the positive electrode of the inductor is connected in sequence to one or more of the fourth and fifth output nodes; and 3) a third mode where the positive electrode of the inductor is connected to the input voltage and the negative electrode of the inductor is connected in sequence to one or more of the first, second and third output nodes.
    Type: Application
    Filed: July 7, 2008
    Publication date: January 7, 2010
    Applicant: ADVANCED ANALOGIC TECHNOLOGIES, INC.
    Inventor: Richard K. Williams
  • ESD protection for bipolar-CMOS-DMOS integrated circuit devices
    Patent number: 7626243
    Abstract: An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: December 1, 2009
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Donald Ray Disney, Jun-Wei Chen, Richard K. Williams, HyungSik Ryu, Wai Tien Chan
  • Modular CMOS analog integrated circuit and power technology
    Patent number: 7608895
    Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: October 27, 2009
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chen
  • High-voltage depletion mode MOSFET
    Patent number: 7605428
    Abstract: All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: October 20, 2009
    Assignee: Advanced Analogic Technologies, Inc.
    Inventors: Richard K. Williams, Donald Ray Disney
  • Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology
    Patent number: 7605432
    Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: October 20, 2009
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chen
  • Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology
    Patent number: 7605433
    Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: October 20, 2009
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chen