Patents by Inventor Richard K. Williams
Richard K. Williams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7485498Abstract: Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package.Type: GrantFiled: February 2, 2007Date of Patent: February 3, 2009Assignee: GEM Services, Inc.Inventors: James Harnden, Allen K. Lam, Richard K. Williams, Anthony Chia, Chu Weibing
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Publication number: 20090010035Abstract: A freewheeling MOSFET is connected in parallel with the inductor in a switched DC/DC converter. When the freewheeling MOSFET is turned on during the switching operation of the converter, while the low-side and energy transfer MOSFETs are turned off, the inductor current circulates or “freewheels” through the freewheeling MOSFET. The frequency of the converter is thereby made independent of the lengths of the magnetizing and energy transfer stages, allowing far greater flexibility in operating and converter and overcoming numerous problems associated with conventional DC/DC converters. For example, the converter may operate in either step-up or step-down mode and may even transition for one mode to the other as the values of the input voltage and desired output voltage vary.Type: ApplicationFiled: April 21, 2008Publication date: January 8, 2009Applicant: Advanced Analogic Technologies, Inc.Inventor: Richard K. Williams
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Publication number: 20090002881Abstract: A damped assembly is provided including a drivable assembly with housing, and a damper structure in operative association with the housing for dampening noise and/or vibration. The damper structure includes a viscoelastic damper layer and a continuous, polymeric constraining layer intimately contacting and encasing the viscoelastic damper layer.Type: ApplicationFiled: June 23, 2008Publication date: January 1, 2009Inventors: Daniel E. Boss, Richard K. Williams
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Publication number: 20080290449Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.Type: ApplicationFiled: July 30, 2008Publication date: November 27, 2008Applicant: Advanced Analogic Technologies, Inc.Inventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
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Publication number: 20080291711Abstract: A freewheeling DC/DC step-down converter includes a high-side MOSFET, an inductor and an output capacitor connected between the input voltage and ground. A freewheeling clamp, which includes a freewheeling MOSFET and diode, is connected across the inductor. When the high-side MOSFET is turned off, a current circulates through the inductor and freewheeling clamp rather than to ground, improving the efficiency of the converter. The converter has softer diode recovery and less voltage overshoot and noise than conventional Buck converters and features unique benefits during light-load conditions.Type: ApplicationFiled: April 21, 2008Publication date: November 27, 2008Applicant: Advanced Analogic Technologies, Inc.Inventor: Richard K. Williams
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Publication number: 20080290452Abstract: A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density of the devices can be increased. Also trench constrained doped region diffuse faster and deeper than unconstrained diffusions, thereby reducing the time and temperature needed to complete a desired depth diffusion. The technique may be used for semiconductor devices such as bipolar transistors as well as isolation regions that electrically isolate the devices from each other. In one group of embodiments, a buried layer is formed at an interface between an epitaxial layer and a substrate, at a location generally below the dopant in the mesa.Type: ApplicationFiled: July 31, 2008Publication date: November 27, 2008Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
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Publication number: 20080290450Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.Type: ApplicationFiled: July 30, 2008Publication date: November 27, 2008Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
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Publication number: 20080290451Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.Type: ApplicationFiled: July 30, 2008Publication date: November 27, 2008Applicant: Advanced Analogic Technologies, Inc.Inventors: Richard K. Williams, Donald Ray Disney, Jun-Wei Chen, Wal Tien Chan, HyungSik Ryu
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Publication number: 20080293214Abstract: A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density of the devices can be increased. Also trench constrained doped region diffuse faster and deeper than unconstrained diffusions, thereby reducing the time and temperature needed to complete a desired depth diffusion. The technique may be used for semiconductor devices such as bipolar transistors as well as isolation regions that electrically isolate the devices from each other. In one group of embodiments, a buried layer is formed at an interface between an epitaxial layer and a substrate, at a location generally below the dopant in the mesa.Type: ApplicationFiled: July 31, 2008Publication date: November 27, 2008Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
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Publication number: 20080290911Abstract: A gate driver for a power MOSFET in, for example, a DC-DC converter switches the MOSFET between a fully-on condition and a low-current condition instead of switching the MOSFET between fully-on and fully-off conditions. The amount of charge that must be transferred to charge and discharge the gate of the MOSFET is thereby reduced, and the efficiency of the MOSFET is improved. A feedback circuit may be used to assure that the magnitude of current in the power MOSFET in its low-current condition is correct. Alternatively, a trimming process may be used to correct the magnitude of the voltage supplied by the gate driver to the gate of the power MOSFET in the low-current condition.Type: ApplicationFiled: August 8, 2007Publication date: November 27, 2008Applicant: Advanced Analogic Technologies, Inc.Inventor: Richard K. Williams
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Patent number: 7449380Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.Type: GrantFiled: February 25, 2005Date of Patent: November 11, 2008Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
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Patent number: 7445979Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall and which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.Type: GrantFiled: April 5, 2006Date of Patent: November 4, 2008Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
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Publication number: 20080254592Abstract: Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths.Type: ApplicationFiled: April 30, 2008Publication date: October 16, 2008Applicant: Advanced Analogic Technologies, Inc.Inventor: Richard K. Williams
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Publication number: 20080252372Abstract: A stereo class-D audio system includes a first die including four monolithically integrated NMOS high-side devices and a second a second die including four monolithically integrated PMOS low-side devices. The audio system also includes a set of electrical contacts for connecting the high and low-side devices to components within the a stereo class-D audio system, the set of electrical contacts including at least one supply contact for connecting the drains of the high-side devices to a supply voltage (Vcc) and at least one ground contact for connecting the drains of the low-side devices to ground, the electrical contacts also including respective contacts for each source of the high and low-side devices allowing the source of each high-side device to be connected to the source of a respective low-side device to form two H-bridge circuits.Type: ApplicationFiled: October 17, 2007Publication date: October 16, 2008Applicant: ADVANCED ANALOGIC TECHNOLOGIES, INC.Inventor: Richard K. Williams
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Patent number: 7432555Abstract: A semiconductor die has a bonding pad for a MOSFET such as a power MOSFET and a separate bonding pad for ESD protection circuitry. Connecting the bonding pads together makes the ESD protection circuitry functional to protect the MOSFET. Before connecting the bonding pads together, the ESD protection circuitry and/or the MOSFET can be separately tested. A voltage higher than functioning ESD protection circuitry would permit can be used when testing the MOSFET. A packaging process such as wire bonding or attaching the die to a substrate in a flip-chip package can connect the bonding pads after testing.Type: GrantFiled: May 5, 2005Date of Patent: October 7, 2008Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
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Publication number: 20080237656Abstract: An isolation structure for a semiconductor device comprises a floor isolation region, a dielectric filled trench above the floor isolation region and a sidewall isolation region extending downward from the bottom of the trench to the floor isolation region. This structure provides a relatively deep isolated pocket in a semiconductor substrate while limiting the depth of the trench that must be etched in the substrate. An isolated junction field-effect transistor is formed in the isolated pocket.Type: ApplicationFiled: December 17, 2007Publication date: October 2, 2008Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
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Publication number: 20080237706Abstract: A lateral MOSFET formed in a substrate of a first conductivity type includes a gate formed atop a gate dielectric layer over a surface of the substrate, a drain region of a second conductivity type, a source region of a second conductivity type, and a body region of the first conductivity type which extends under the gate. The body region may have a non-monotonic vertical doping profile with a portion located deeper in the substrate having a higher doping concentration than a portion located shallower in the substrate. The lateral MOSFET may be drain-centric, with the source region and an optional dielectric-filled trench surrounding the drain region.Type: ApplicationFiled: December 17, 2007Publication date: October 2, 2008Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
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Publication number: 20080237783Abstract: A bipolar transistor is formed in an isolation structure comprising a floor isolation region, a dielectric filled trench above the floor isolation region and a sidewall isolation region extending downward from the bottom of the trench to the floor isolation region. This structure provides a relatively deep isolated pocket in a semiconductor substrate while limiting the depth of the trench that must be etched in the substrate.Type: ApplicationFiled: December 17, 2007Publication date: October 2, 2008Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
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Publication number: 20080237782Abstract: An isolated diode comprises a floor isolation region, a dielectric-filled trench and a sidewall region extending from a bottom of the trench at least to the floor isolation region. The floor isolation region, dielectric-filled trench and a sidewall region are comprised in one terminal (anode or cathode) of the diode and together form an isolated pocket in which the other terminal of the diode is formed. In one embodiment the terminals of the diode are separated by a second dielectric-filled trench and sidewall region.Type: ApplicationFiled: December 17, 2007Publication date: October 2, 2008Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
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Publication number: 20080237704Abstract: An isolation structure for a semiconductor device comprises a floor isolation region, a dielectric filled trench above the floor isolation region and a sidewall isolation region extending downward from the bottom of the trench to the floor isolation region. This structure provides a relatively deep isolated pocket in a semiconductor substrate while limiting the depth of the trench that must be etched in the substrate. A MOSFET is formed in the isolated pocket.Type: ApplicationFiled: December 17, 2007Publication date: October 2, 2008Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
