Patents by Inventor Richard K. Williams

Richard K. Williams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method Of Starting DC/DC Converter Using Synchronous Freewheeling MOSFET
    Publication number: 20110248691
    Abstract: A DC/DC converter including an inductor and a capacitor is started by connecting an input voltage to the inductor and shunting a current around the inductor so as to pre-charge the capacitor to a predetermined voltage.
    Type: Application
    Filed: June 22, 2011
    Publication date: October 13, 2011
    Applicant: ADVANCED ANALOGIC TECHNOLOGIES, INC.
    Inventor: Richard K. Williams
  • Step-down switching regulator with freewheeling diode
    Patent number: 8035364
    Abstract: A freewheeling DC/DC step-down converter includes a high-side MOSFET, an inductor and an output capacitor connected between the input voltage and ground. A freewheeling clamp, which includes a freewheeling MOSFET and diode, is connected across the inductor. When the high-side MOSFET is turned off, a current circulates through the inductor and freewheeling clamp rather than to ground, improving the efficiency of the converter. The converter has softer diode recovery and less voltage overshoot and noise than conventional Buck converters and features unique benefits during light-load conditions.
    Type: Grant
    Filed: April 21, 2008
    Date of Patent: October 11, 2011
    Assignee: Advanced Analogic Technologies, Inc.
    Inventor: Richard K. Williams
  • Isolated rectifier diode
    Patent number: 8030731
    Abstract: An isolated diode comprises a floor isolation region, a dielectric-filled trench and a sidewall region extending from a bottom of the trench at least to the floor isolation region. The floor isolation region, dielectric-filled trench and a sidewall region are comprised in one terminal (anode or cathode) of the diode and together form an isolated pocket in which the other terminal of the diode is formed. In one embodiment the terminals of the diode are separated by a second dielectric-filled trench and sidewall region.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: October 4, 2011
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
  • Method of fabricating trench-constrained isolation diffusion for semiconductor devices
    Patent number: 8030152
    Abstract: A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density of the devices can be increased. Also trench constrained doped region diffuse faster and deeper than unconstrained diffusions, thereby reducing the time and temperature needed to complete a desired depth diffusion. The technique may be used for semiconductor devices such as bipolar transistors as well as isolation regions that electrically isolate the devices from each other. In one group of embodiments, a buried layer is formed at an interface between an epitaxial layer and a substrate, at a location generally below the dopant in the mesa.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: October 4, 2011
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
  • Method Of Sensing Magnitude Of Current Through Semiconductor Power Device
    Publication number: 20110221421
    Abstract: A cascode current sensor includes a main MOSFET and a sense MOSFET. The drain terminal of the main MOSFET is connected to a power device whose current is to be monitored, and the source and gate terminals of the main MOSFET are connected to the source and gate terminals, respectively, of the sense MOSFET. The drain voltages of the main and sense MOSFETs are equalized, in one embodiment by using a variable current source and negative feedback. The gate width of the main MOSFET is typically larger than the gate width of the sense MOSFET. Using the size ratio of the gate widths, the current in the main MOSFET is measured by sensing the magnitude of the current in the sense MOSFET. Inserting the relatively large MOSFET in the power circuit minimizes power loss.
    Type: Application
    Filed: May 23, 2011
    Publication date: September 15, 2011
    Inventor: Richard K. Williams
  • Processes For Forming Isolation Structures For Integrated Circuit Devices
    Publication number: 20110201171
    Abstract: Processes for forming isolation structures for semiconductor devices include forming a submerged floor isolation region and a filed trench which together enclose an isolated pocket of the substrate. One process aligns the trench to the floor isolation region. In another process a second, narrower trench is formed in the isolated pocket and filled with a dielectric material while the dielectric material is deposited so as to line the walls and floor of the first trench. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.
    Type: Application
    Filed: April 27, 2011
    Publication date: August 18, 2011
    Applicant: ADVANCED ANALOGIC TECHNOLOGIES, INC.
    Inventors: Donald R. Disney, Richard K. Williams
  • Single Wire Serial Interface
    Publication number: 20110202787
    Abstract: A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock pulses sent to the EN/SET input pin. The output of the counter is passed to a ROM or other decoder circuit. The ROM selects an operational state for the device that corresponds to the value of the counter. In this way, control states may be selected for the device by sending corresponding clock pulses to the EN/SET pin. Holding the EN/SET pin high causes the device to maintain its operational state. Holding the EN/SET pin low for a predetermined timeout period resets the counter and causes the device to adopt a predetermined configuration (such as off) until new clock pulses are received at the EN/SET pin.
    Type: Application
    Filed: February 15, 2011
    Publication date: August 18, 2011
    Inventors: Kevin P. D'Angelo, David Alan Brown, John Sung K. So, Jan Nilsson, Richard K. Williams
  • MOSFET gate drive with reduced power loss
    Patent number: 7994827
    Abstract: A gate driver for a power MOSFET in, for example, a DC-DC converter switches the MOSFET between a fully-on condition and a low-current condition instead of switching the MOSFET between fully-on and fully-off conditions. The amount of charge that must be transferred to charge and discharge the gate of the MOSFET is thereby reduced, and the efficiency of the MOSFET is improved. A trimming process is used to adjust the magnitude of the voltage supplied by the gate driver to the gate of the power MOSFET in the low-current condition.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: August 9, 2011
    Assignee: Advanced Analogic Technologies, Inc.
    Inventor: Richard K. Williams
  • ESD protection for bipolar-CMOS-DMOS integrated circuit devices
    Patent number: 7994578
    Abstract: An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: August 9, 2011
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong)
    Inventors: Donald Ray Disney, Jun-Wei Chen, Richard K. Williams, HyungSik Ryu, Wai Tien Chan
  • Isolation structure for semiconductor integrated circuit substrate
    Patent number: 7994605
    Abstract: Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: August 9, 2011
    Assignee: Advanced Analogic Technologies, Inc.
    Inventor: Richard K. Williams
  • Step-up DC/DC voltage converter with improved transient current capability
    Patent number: 7977927
    Abstract: A DC/DC voltage converter includes an inductive switching voltage regulator and a capacitive charge pump connected in series between the input and output terminals of the converter. The charge pump has a second input terminal connected to the input terminal of the converter. This reduces the series resistance in the current path by which charge is transferred from the capacitor in the charge pump to the output capacitor and thereby improves the ability of the converter to respond to rapid changes in current required by the load.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: July 12, 2011
    Assignee: Advanced Analogic Technologies, Inc.
    Inventor: Richard K. Williams
  • Boost and up-down switching regulator with synchronous freewheeling MOSFET
    Patent number: 7977926
    Abstract: A freewheeling MOSFET is connected in parallel with the inductor in a switched DC/DC converter. When the freewheeling MOSFET is turned on during the switching operation of the converter, while the low-side and energy transfer MOSFETs are turned off, the inductor current circulates or “freewheels” through the freewheeling MOSFET. The frequency of the converter is thereby made independent of the lengths of the magnetizing and energy transfer stages, allowing far greater flexibility in operating and converter and overcoming numerous problems associated with conventional DC/DC converters. For example, the converter may operate in either step-up or step-down mode and may even transition for one mode to the other as the values of the input voltage and desired output voltage vary.
    Type: Grant
    Filed: April 21, 2008
    Date of Patent: July 12, 2011
    Assignee: Advanced Analogic Technologies, Inc.
    Inventor: Richard K. Williams
  • Cascode current sensor for discrete power semiconductor devices
    Patent number: 7960997
    Abstract: A cascode current sensor includes a main MOSFET and a sense MOSFET. The drain terminal of the main MOSFET is connected to a power device whose current is to be monitored, and the source and gate terminals of the main MOSFET are connected to the source and gate terminals, respectively, of the sense MOSFET. The drain voltages of the main and sense MOSFETs are equalized, in one embodiment by using a variable current source and negative feedback. The gate width of the main MOSFET is typically larger than the gate width of the sense MOSFET. Using the size ratio of the gate widths, the current in the main MOSFET is measured by sensing the magnitude of the current in the sense MOSFET. Inserting the relatively large MOSFET in the power circuit minimizes power loss.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: June 14, 2011
    Assignee: Advanced Analogic Technologies, Inc.
    Inventor: Richard K. Williams
  • Method of forming isolation structure for semiconductor integrated circuit substrate
    Patent number: 7955947
    Abstract: Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: June 7, 2011
    Assignee: Advanced Analogic Technologies, Inc.
    Inventor: Richard K. Williams
  • Isolated junction field-effect transistor
    Patent number: 7956391
    Abstract: Various integrated circuit devices, in particular a junction field-effect transistor (JFET), are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described.
    Type: Grant
    Filed: February 27, 2008
    Date of Patent: June 7, 2011
    Assignee: Advanced Analogic Technologies, Inc.
    Inventors: Donald R. Disney, Richard K. Williams
  • Isolation structures for integrated circuits
    Patent number: 7956437
    Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: June 7, 2011
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Donald Ray Disney, Jun-Wei Chen, Wai Tien Chan, HyungSik Ryu
  • Processes for forming isolation structures for integrated circuit devices
    Patent number: 7939420
    Abstract: Processes for forming isolation structures for semiconductor devices include forming a submerged floor isolation region and a filed trench which together enclose an isolated pocket of the substrate. One process aligns the trench to the floor isolation region. In another process a second, narrower trench is formed in the isolated pocket and filled with a dielectric material while the dielectric material is deposited so as to line the walls and floor of the first trench. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: May 10, 2011
    Assignee: Advanced Analogic Technologies, Inc.
    Inventors: Donald R. Disney, Richard K. Williams
  • Semiconductor integrated circuit substrate containing isolation structures
    Patent number: 7923821
    Abstract: Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: April 12, 2011
    Assignee: Advanced Analogic Technologies, Inc.
    Inventor: Richard K. Williams
  • Single wire serial interface
    Patent number: 7921320
    Abstract: A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock pulses sent to the EN/SET input pin. The output of the counter is passed to a ROM or other decoder circuit. The ROM selects an operational state for the device that corresponds to the value of the counter. In this way, control states may be selected for the device by sending corresponding clock pulses to the EN/SET pin. Holding the EN/SET pin high causes the device to maintain its operational state. Holding the EN/SET pin low for a predetermined timeout period resets the counter and causes the device to adopt a predetermined configuration (such as off) until new clock pulses are received at the EN/SET pin.
    Type: Grant
    Filed: October 17, 2006
    Date of Patent: April 5, 2011
    Assignee: Advanced Analogic Technologies, Inc.
    Inventors: Kevin P. D'Angelo, David Alan Brown, John Sung K. So, Jan Nilsson, Richard K Williams
  • Method of forming isolation structure for semiconductor integrated circuit substrate
    Patent number: 7915137
    Abstract: Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: March 29, 2011
    Assignee: Advanced Analogic Technologies, Inc.
    Inventor: Richard K. Williams