Patents by Inventor Richard L. Galbraith

Richard L. Galbraith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10592334
    Abstract: A data storage device is disclosed comprising a non-volatile storage medium (NVSM), wherein a plurality of codewords and corresponding parity sector are written to the NVSM and then read from the NVSM. Each codeword read from the NVSM is processed using a Viterbi-type detector, thereby generating codeword reliability metrics. The codeword reliability metrics for at least some of the codewords are processed using a low density parity check (LDPC) type decoder, thereby generating a LDPC reliability metric for each symbol of at least one codeword. The LDPC reliability metrics for at least one of an un-converged codeword are processed using the parity sector, thereby updating the un-converged codeword reliability metrics. Processing the codeword reliability metrics with the LDPC decoder and updating the reliability metrics with the parity sector is repeated at least once before updating the LDPC reliability metrics of at least the un-converged codeword using the Viterbi-type detector.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: March 17, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Iouri Oboukhov, Niranjay Ravindran, Richard L. Galbraith
  • Patent number: 10530390
    Abstract: A data storage device is disclosed comprising a head actuated over a disk comprising a data track having at least a first data segment and a second data segment. A first plurality of codewords are generated, and a first parity sector is generated over the first plurality of codewords. The first plurality of codewords and the first parity sector are written to the first data segment. A second plurality of codewords are generated, and a second parity sector is generated over the second plurality of codewords. The second plurality of codewords and the second parity sector are written to the second data segment. During a read operation the data segments of the data track are processed sequentially to decode the codewords using a low density parity check (LDPC) decoder, wherein the reliability metrics of un-converged codewords are stored in a codeword buffer and updated using the respective parity sector.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: January 7, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Iouri Oboukhov, Weldon M. Hanson, Niranjay Ravindran, Richard L. Galbraith
  • Publication number: 20190356334
    Abstract: A data storage device is disclosed comprising a head actuated over a disk comprising a data track having at least a first data segment and a second data segment. A first plurality of codewords are generated, and a first parity sector is generated over the first plurality of codewords. The first plurality of codewords and the first parity sector are written to the first data segment. A second plurality of codewords are generated, and a second parity sector is generated over the second plurality of codewords. The second plurality of codewords and the second parity sector are written to the second data segment. During a read operation the data segments of the data track are processed sequentially to decode the codewords using a low density parity check (LDPC) decoder, wherein the reliability metrics of un-converged codewords are stored in a codeword buffer and updated using the respective parity sector.
    Type: Application
    Filed: May 17, 2018
    Publication date: November 21, 2019
    Inventors: IOURI OBOUKHOV, WELDON M. HANSON, NIRANJAY RAVINDRAN, RICHARD L. GALBRAITH
  • Publication number: 20190354430
    Abstract: A data storage device is disclosed comprising a non-volatile storage medium (NVSM), wherein a plurality of codewords and corresponding parity sector are written to the NVSM and then read from the NVSM. Each codeword read from the NVSM is processed using a Viterbi-type detector, thereby generating codeword reliability metrics. The codeword reliability metrics for at least some of the codewords are processed using a low density parity check (LDPC) type decoder, thereby generating a LDPC reliability metric for each symbol of at least one codeword. The LDPC reliability metrics for at least one of an un-converged codeword are processed using the parity sector, thereby updating the un-converged codeword reliability metrics. Processing the codeword reliability metrics with the LDPC decoder and updating the reliability metrics with the parity sector is repeated at least once before updating the LDPC reliability metrics of at least the un-converged codeword using the Viterbi-type detector.
    Type: Application
    Filed: May 17, 2018
    Publication date: November 21, 2019
    Inventors: IOURI OBOUKHOV, NIRANJAY RAVINDRAN, RICHARD L. GALBRAITH
  • Patent number: 10417089
    Abstract: A data storage device is disclosed comprising a non-volatile storage medium (NVSM). A reliability metric for each symbol of each of a plurality of codewords read from the NVSM is generated, and a number of erasures for a first codeword are generated, wherein the number of erasures exceeds the correction power of the first codeword. A reliability metric of the first codeword is modified corresponding to one of the erasures. The reliability metrics for each codeword including the modified reliability metrics of the first codeword are first iteratively processed using a low density parity check (LDPC) type decoder, thereby first updating the reliability metric for each symbol of each codeword. The reliability metrics for the first codeword are second updated using the parity sector, and the second updated reliability metrics for the first codeword are second iteratively processed using the LDPC-type decoder.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: September 17, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Iouri Oboukhov, Weldon M. Hanson, Niranjay Ravindran, Richard L. Galbraith
  • Publication number: 20190250987
    Abstract: A data storage device is disclosed comprising a non-volatile storage medium (NVSM). A reliability metric for each symbol of each of a plurality of codewords read from the NVSM is generated, and a number of erasures for a first codeword are generated, wherein the number of erasures exceeds the correction power of the first codeword. A reliability metric of the first codeword is modified corresponding to one of the erasures. The reliability metrics for each codeword including the modified reliability metrics of the first codeword are first iteratively processed using a low density parity check (LDPC) type decoder, thereby first updating the reliability metric for each symbol of each codeword. The reliability metrics for the first codeword are second updated using the parity sector, and the second updated reliability metrics for the first codeword are second iteratively processed using the LDPC-type decoder.
    Type: Application
    Filed: February 13, 2018
    Publication date: August 15, 2019
    Inventors: IOURI OBOUKHOV, WELDON M. HANSON, NIRANJAY RAVINDRAN, RICHARD L. GALBRAITH
  • Patent number: 9632863
    Abstract: In general, techniques are described for performing track-error-correcting code on data. A hard drive comprising a storage device and a read channel may be configured to perform the techniques. The read channel may be configured to read data from a track comprising a plurality of data sectors each comprising a plurality of bits, and a parity sector comprising a plurality of parity bits, wherein the data includes a plurality of bit groups, each bit group including a single bit from each data sector, and wherein each parity bit corresponds to a respective bit group, perform a track parity check, and, responsive to determining that the data includes an error, identify one or more data sectors as possible sources of the at least one error and adjust a log-likelihood ratio for at least one bit from the bit group.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: April 25, 2017
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Richard L. Galbraith, Weldon M. Hanson, Roger W. Wood
  • Publication number: 20160203041
    Abstract: In general, techniques are described for performing track-error-correcting code on data. A hard drive comprising a storage device and a read channel may be configured to perform the techniques. The read channel may be configured to read data from a track comprising a plurality of data sectors each comprising a plurality of bits, and a parity sector comprising a plurality of parity bits, wherein the data includes a plurality of bit groups, each bit group including a single bit from each data sector, and wherein each parity bit corresponds to a respective bit group, perform a track parity check, and, responsive to determining that the data includes an error, identify one or more data sectors as possible sources of the at least one error and adjust a log-likelihood ratio for at least one bit from the bit group.
    Type: Application
    Filed: January 13, 2015
    Publication date: July 14, 2016
    Inventors: Richard L. Galbraith, Weldon M. Hanson, Roger W. Wood
  • Patent number: 8276038
    Abstract: A data storage system includes an encoder subsystem comprising an error correction code encoder, a modulation encoder, and a precoder, and a decoder subsystem similarly comprising a detector, an inverse precoder, a channel decoder, and an error correction code decoder. The error correction encoder applies an error correction code to the incoming user bit stream, and the modulation encoder applies so-called modulation or constrained coding to the error correction coded bit stream. The precoder applies so-called preceding to the modulation encoded bit stream. However, this preceding is applied to selected portions of the bit stream only. There can also be a permutation step where the bit sequence is permuted after the modulation encoder before preceding is applied by the precoder. The decoder subsystem operates in the inverse manner.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: September 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Roy D. Cideciyan, Ajay Dholakia, Evangelos S. Eleftheriou, Richard L. Galbraith, Weldon M. Hanson, Thomas Mittelholzer, Travis R. Oenning
  • Patent number: 7694205
    Abstract: A method and apparatus for providing a read channel having combined parity and non-parity post processing is disclosed. A post-processor combines parity and non-parity post processing to make both parity and non-parity corrections so that error events that cannot be detected by parity may be corrected. Non-parity detectable error events are only kept for consideration if their likelihood is above a set threshold.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: April 6, 2010
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Roy D. Cideciyan, Ajay Dholakia, Evangelos S. Eleftheriou, Richard L. Galbraith, Weldon M. Hanson, Thomas Mittelholzer, Travis R. Oenning
  • Patent number: 7395482
    Abstract: A data storage system includes an encoder subsystem comprising an error correction code encoder, a modulation encoder, and a precoder, and a decoder subsystem similarly comprising a detector, an inverse precoder, a channel decoder, and an error correction code decoder. The error correction encoder applies an error correction code to the incoming user bit stream, and the modulation encoder applies so-called modulation or constrained coding to the error correction coded bit stream. The precoder applies so-called precoding to the modulation encoded bit stream. However, this precoding is applied to selected portions of the bit stream only. There can also be a permutation step where the bit sequence is permuted after the modulation encoder before precoding is applied by the precoder. The decoder subsystem operates in the inverse manner.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: July 1, 2008
    Assignee: International Business Machines Corporation
    Inventors: Roy D. Cideciyan, Ajay Dholakia, Evangelos S. Eleftheriou, Richard L. Galbraith, Weldon M. Hanson, Thomas Mittelholzer, Travis R. Oenning
  • Patent number: 7286595
    Abstract: An apparatus that uses a lengthened equalization target filter with a matched filter metric in a Viterbi detector is disclosed. The equalization target includes a base partial response component, i.e., (1?D2), a fractional coefficient polynomial component to whiten the noise, i.e., (1+p1D+p2D2), and a time-reversed replica of the noise-whitening component. Thus, the time-reversed replica of the noise-whitening component comes from what was formerly a matched filter component.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: October 23, 2007
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Roy D. Cideciyan, Ajay Dholakia, Evangelos Eleftheriou, Richard L. Galbraith, Thomas Mittelholzer, Travis R. Oenning
  • Patent number: 7245444
    Abstract: A method and apparatus for providing a read channel having imbedded channel signal analysis is disclosed. The method and apparatus disclosed determines the types of noise present in a read signal and separates different noises out of the read signal. A signal is read from a storage medium and a written signal is removed from the read signal to produce a noise residue signal. The noise residue signal is converted to a power residue signal. The power residue signal is correlated with a Pseudo Random Bit Sequences (PRBS) sequence used to generate the written signal to produce a deconvolved signal. The deconvolved signal is accumulated.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: July 17, 2007
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Richard L. Galbraith, Travis R. Oenning, Eric J. Tree, Bruce A. Wilson
  • Patent number: 7193802
    Abstract: An apparatus for providing dynamic equalizer optimization is disclosed. The present invention solves the above-described problems by providing equalizer coefficient updates that converge towards the same solution as the direct method without having to first write a known pattern to the disk or requiring any prior knowledge of the data already written on the disk. The adaptive cosine function may be used to modify only a DFIR tap set, only the j and k parameters of a cosine equalizer or to modify both the tap set for a DFIR filter and the j and k parameters of the cosine equalizer. Another algorithm, such as the LMS algorithm, may be used to modify parameters not modified by the cosine algorithm.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: March 20, 2007
    Assignee: Hitachi Global Storage Technologies Netherlands, B.V.
    Inventors: Roy D. Cideciyan, Ajay Dholakia, Evangelos S. Eleftheriou, Richard L. Galbraith, Weldon M. Hanson, Thomas Mittelholzer, Travis R. Oenning, Michael J. Ross, David J. Stanek
  • Patent number: 7173784
    Abstract: An apparatus for providing data dependent detection in a data read channel is disclosed. Parameters in a read channel are dynamically adjusted according to data dependent noise. For example, a comparison in an add-compare-select (ACS) unit of a Viterbi decoder may be adjusted or offset terms in error event filters may be biased to choose a Viterbi sequence with more transitions or to compensate for polarity dependent noise.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: February 6, 2007
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Roy D. Cideciyan, Ajay Dholakia, Evangelos Eleftheriou, Richard L. Galbraith, Thomas Mittelholzer, Travis R. Oenning
  • Patent number: 7164371
    Abstract: A method and apparatus for data coding for high-density recording channels exhibiting low frequency contents is disclosed. Coding is used that satisfies both Running Digital Sum (RDS) and Maximum Transition Run (MTR) properties, which are desirable for achieving high-density recording for recording channels exhibiting low frequency components such as perpendicular magnetic recording channel.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: January 16, 2007
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Yuan Xing Lee, Ismail Demirkan, Richard L. Galbraith, Evangelos Eleftheriou, Roy D. Cideciyan
  • Patent number: 6812867
    Abstract: Described is a modulation encoder having a finite state machine for converting input bits into output bits in which the number of alternating output bits is limited to j+1 where j is a predefined maximum number of transitions in the output bits, and in which the number of like output bits is limited to k+1 where k is a predefined maximum number of non-transitions in the output bits. The modulation encoder may be employed in encoding apparatus for converting an input bit stream into an output bit stream. Such apparatus may comprise partitioning logic for partitioning the input bit stream into a first group of bits and a second group of bits. A plurality of the aforementioned modulation encoders may be connected to the partitioning logic for converting the first group of bits into coded output bits. Combining logic may be connected to the or each modulation encoder and the partitioning logic for combining the coded output bits and the second group of bits to generate the output bit stream.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: November 2, 2004
    Assignee: International Business Machines Corp.
    Inventors: Roy D Cideciyan, Ajay Dholakia, Evangelos S Eleftheriou, Richard L Galbraith, Thomas Mittelholzer, Travis R Oenning, David J Stanek
  • Publication number: 20030227397
    Abstract: Described is a modulation encoder having a finite state machine for converting input bits into output bits in which the number of alternating output bits is limited to j+1 where j is a predefined maximum number of transitions in the output bits, and in which the number of like output bits is limited to k+1 where k is a predefined maximum number of non-transitions in the output bits. The modulation encoder may be employed in encoding apparatus for converting an input bit stream into an output bit stream. Such apparatus may comprise partitioning logic for partitioning the input bit stream into a first group of bits and a second group of bits. A plurality of the aforementioned modulation encoders may be connected to the partitioning logic for converting the first group of bits into coded output bits. Combining logic may be connected to the or each modulation encoder and the partitioning logic for combining the coded output bits and the second group of bits to generate the output bit stream.
    Type: Application
    Filed: June 5, 2003
    Publication date: December 11, 2003
    Applicant: International Business Machines Corporation
    Inventors: Roy D. Cideciyan, Ajay Dholakia, Evangelos S. Eleftheriou, Richard L. Galbraith, Thomas Mittelholzer, Travis R. Oenning, David J. Stanek
  • Patent number: 6643814
    Abstract: Maximum transition run encoding of a succession of M-bit data words to produce a succession of N-bit code words, where N→−M, for supply to a magnetic recording channel is described. Each M-bit data word is encoded in accordance with an MTR coding scheme to produce a G-bit word, where N→−G→M, such that the maximum number of consecutive bits of a first value, generally bits of value “1”, in a succession of the G-bit words is limited to a first predetermined value j1. The G-bit word is then encoded to produce an N-bit word in accordance with a second coding scheme.
    Type: Grant
    Filed: May 30, 2000
    Date of Patent: November 4, 2003
    Assignee: International Business Machines Corporation
    Inventors: Roy D. Cideciyan, Jonathan D. Coker, Evangelos S. Eleftheriou, Richard L. Galbraith, Dave James Stanek
  • Patent number: 6625235
    Abstract: In a maximum likelihood sequence detector for symbol sequences which were equalized in a PR4 equalizer, noise prediction means (35) are provided including infinite impulse response (IIR) filtering, which have noise-whitening capabilities and are imbedded into the maximum likelihood detection process. The resulting INPML detector (10) can be implemented in digital or analog circuit technology. In addition, a DC-notch filter (44a) and a stochastic gradient procedure can be provided for DC offset compensation and for MR head or signal asymmetry compensation.
    Type: Grant
    Filed: November 2, 1999
    Date of Patent: September 23, 2003
    Assignee: International Business Machines Corporation
    Inventors: Jonathan D. Coker, Richard L. Galbraith, Evangelos S. Eleftheriou, Walter Hirt