Abstract: Apparatus and method for providing equalization adjustment for a filter are provided in a PRML data channel. A first predetermined test pattern is written. Relative error is measured in both magnitude and phase for predetermined frequencies. A relative magnitude ratio for the predetermined frequencies and a phase delay between the predetermined frequencies are identified. A tap set is generated having predefined frequency responses at a plurality of predefined discrete frequencies.

Abstract: Timing loop apparatus and method are provided for data detection in a partial-response maximum-likelihood (PRML) data channel. The PRML data channel includes an analog to digital converter (ADC) providing samples to a digital filter during a tracking mode and to a gain and timing control during an acquisition mode. Sample values from the ADC are received at peaks and zeros on sync field pattern. An error absolute value is calculated from the received ADC sample values and an error sign of the calculated error absolute valve calculated using a most significant bit of the current and a previous sample. Timing correction values are calculated responsive to the calculated error absolute value and applied to a clock gated register that latches and holds the generated timing correction values for a predefined number of clock cycles.

Abstract: A method and apparatus are provided for adaptive chip trim adjustment for an integrated circuit. A plurality of switching devices have an unswitched state and a switched state. The unswitched state corresponds to one binary value, and the switched state corresponds to another binary value. A first trim word is provided by sensing the switching devices. The switching devices are temporarily bypassed, and an override bit pattern is supplied to simulate any desired pattern of the switching device states. The override bit pattern is used for simulating a switched or unswitched state for each of the plurality of switching devices.

Abstract: The invention provides a circuit and method for performing test procedures on a data storage and recovery system for a magnetic storage unit. Error sample values from a read operator in a data storage and recovery system are applied to a first and a second process path to generate output signals. A source of level samples of a logical data level is also provided. The first process path generates an output signal comprising a square of each error value sample. The second process path compares the error value samples and a compare level and generates an output signal comprising a result of each comparison. The output signal of the first process path, the second process path, or the level samples is selected and is associated with a data type. In response to a coincidence of a data type associated with a selected signal with a desired data type, the selected signal is gated and then accumulated. The window during which the selected signal is accumulated may vary.

Abstract: A method and apparatus are provided for determining an adjustable precompensation value in a partial-response maximum-likelihood (PRML) data channel. The PRML data channel includes an adjustable precompensation function for modulating the write data waveform. A predetermined test pattern is written using write circuitry in the disk file. The predetermined test pattern is insensitive to channel misequalization and provides a reference for gain and timing control. The written predetermined test pattern is read back using read circuitry in the disk file. An error in sample values in the read back predetermined test pattern is identified using logic provided in the PRML data channel while performing a standard read operation of a data sector written with the test pattern. The adjustable write precompensation value is adjusted responsive to identifying an error.

Abstract: Apparatus and method for providing equalization adjustment for a finite impulse response (FIR) digital filter are provided in a PRML data channel. A plurality of transformations are defined to transform effective tap weights in a digital filter into modified effective tap weight values by adding each said initial effective tap weight value with a selected cosine equalization adjustment function. A cosine expander circuit is provided for expanding 8-byte compressed equalizations into a 32-byte format and for altering the filter response by a selected cosine equalization adjustment function.

Abstract: A 10-tap finite impulse response (FIR) digital filter is provided in a partial response signaling and maximum-likelihood (PRML) data channel. A plurality of partial sums of predetermined tap weights are stored in a palette random access memory (RAM). A fixed qualifier value is received and used together with selected ones of the stored partial sums for calculating a predetermined tap weight. Predetermined filter coefficients are calculated and stored in a filter RAM using the calculated predetermined tap weight and predefined ones of the stored partial sums.

Abstract: Apparatus and method for asynchronous servo identification (SID)/address mark detection are provided for data detection in a partial-response maximum-likelihood (PRML) data channel. The SID/AM pattern includes a first preamble section defined by a plurality of short magnets; a body section defined by a predetermined number of long magnets; and a delimiter section defined by a plurality of short magnets. Samples from the digital filter are applied to first and second correlation filtering paths. The first correlation filtering path includes a polarity threshold function to indicate one of a preamble section or a delimiter section of a SID/AM pattern. The second correlation filtering paths includes a second threshold function and a comparator for sequentially comparing sequential ones of the received samples responsive to identifying the second threshold value to identify a predefined sequence.

Abstract: A method and apparatus for modulating a data reference clock for rotational speed variations of the data storage disk in a direct access data storage file. A data reference clock is generated from an encoded disk rate clock of the data file. A readback signal from at least one predetermined region of the disk surface is sensed and a sync byte is detected responsive to the readback signal. An early window control signal and a late window control signal are generated corresponding to end boundaries for capturing readback encoded data signals. A load complete signal is identified responsive to the readback signal. The identified load complete signal with the early window control signal and the late window control signal and the generated data reference clock is adjusted responsive to overlapping compared signals.

Abstract: Apparatus and method of thermal asperity compensation are provided for data detection in a partial-response maximum-likelihood (PRML) data channel. The PRML data channel includes an analog to digital converter (ADC) having a normal operating range and a filter, gain and timing control coupled to the ADC. When a thermal asperity is detected, a thermal asperity recovery mode is established responsive to the detected thermal asperity. The gain and timing control are held and the normal operating range of the ADC is adjusted responsive to the thermal asperity recovery mode. Also an AC coupling pole frequency is elevated responsive to the thermal asperity recovery mode.

Abstract: A method and apparatus are provided for controlling a digital filter function included in a data path within gain and timing control loops of a PRML magnetic recording channel. The digital filter function is removed from the data path during an acquisition mode and the digital filter function is restored to the data path during a tracking mode. A predetermined gain and a quantized delay at a synchronization frequency are provided when switching from acquisition mode to tracking mode. A unity gain and a delay of an integer number of sample periods are provided at a synchronization frequency when switching from acquisition mode to tracking mode.

Abstract: Apparatus and methods are provided for encoding a predefined number of bits of binary data into codewords having a predefined number of bits for a partial-response maximum-liklihood (PRML) data channel in a direct access storage device (DASD). Rate 8/9 block codes having maximum ones and run length constraints (0,8,12,.infin.) and (0,8,6,.infin.) provide timing and gain control and reduced susceptibility to misequalization effects in PRML channels.

Abstract: A method and apparatus are provided for measuring flying height changes of a transducer head relative to a disk surface of a rotating disk in a disk file. A predetermined pattern is written on at least one predetermined region of the disk file. The predetermined region is normally not rewritten during operation of the disk file. At least one readback signal is sensed from at least one predetermined region of the disk surface. A plurality of sample values are identified corresponding to each readback signal. A change in the flying height is calculated utilizing the identified sample values. A frequency equalization number K can be utilized to calculate the magnitude and sign of the flying height change. Alternatively, real-time digital analysis of a predetermined pattern written on at least one predetermined region of the disk surface can be utilized to calculate the magnitude and sign of the flying height change.

Abstract: Data byte fields and corresponding ECC byte fields to be magnetically recorded as multi-byte records is randomized prior to run-length encoding. The randomized/encoded data is then written. When the randomized/encoded data is read back, the data is first decoded, and then derandomized in a complementary fashion. The randomizing avoids the writing of byte patterns that tend to stress the ability of a head/disk interface to record the data transitions at proper linear track positions. When reading, the complementary derandomizing scheme avoids presenting a repeating pattern of read-errors to the ECC network. Thus, read-errors are not propagated through the read channel. Data is randomized, and subsequently derandomized, in a repeating or pseudo random, complementary sequence for each byte. The complementary randomizing/derandomizing sequence is determined by the count contained in a counter.

Abstract: A circuit for a partial-response, maximum likelihood (PRML) magnetic recording channel stretches and shrinks pulses in particular write-data sequences. The circuit maintains precise tracking in the delays among multiple signals by sending them through the same number of identical circuits on the same chip. An external digital code varies the amount of delay in a clock signal so as to stretch and shrink the data pulses by different amounts.