Abstract: A data storage system includes an encoder subsystem comprising an error correction code encoder, a modulation encoder, and a precoder, and a decoder subsystem similarly comprising a detector, an inverse precoder, a channel decoder, and an error correction code decoder. The error correction encoder applies an error correction code to the incoming user bit stream, and the modulation encoder applies so-called modulation or constrained coding to the error correction coded bit stream. The precoder applies so-called preceding to the modulation encoded bit stream. However, this preceding is applied to selected portions of the bit stream only. There can also be a permutation step where the bit sequence is permuted after the modulation encoder before preceding is applied by the precoder. The decoder subsystem operates in the inverse manner.

Abstract: A method and apparatus for providing a read channel having combined parity and non-parity post processing is disclosed. A post-processor combines parity and non-parity post processing to make both parity and non-parity corrections so that error events that cannot be detected by parity may be corrected. Non-parity detectable error events are only kept for consideration if their likelihood is above a set threshold.

Abstract: A data storage system includes an encoder subsystem comprising an error correction code encoder, a modulation encoder, and a precoder, and a decoder subsystem similarly comprising a detector, an inverse precoder, a channel decoder, and an error correction code decoder. The error correction encoder applies an error correction code to the incoming user bit stream, and the modulation encoder applies so-called modulation or constrained coding to the error correction coded bit stream. The precoder applies so-called precoding to the modulation encoded bit stream. However, this precoding is applied to selected portions of the bit stream only. There can also be a permutation step where the bit sequence is permuted after the modulation encoder before precoding is applied by the precoder. The decoder subsystem operates in the inverse manner.

Abstract: An apparatus that uses a lengthened equalization target filter with a matched filter metric in a Viterbi detector is disclosed. The equalization target includes a base partial response component, i.e., (1?D2), a fractional coefficient polynomial component to whiten the noise, i.e., (1+p1D+p2D2), and a time-reversed replica of the noise-whitening component. Thus, the time-reversed replica of the noise-whitening component comes from what was formerly a matched filter component.

Abstract: A method and apparatus for providing a read channel having imbedded channel signal analysis is disclosed. The method and apparatus disclosed determines the types of noise present in a read signal and separates different noises out of the read signal. A signal is read from a storage medium and a written signal is removed from the read signal to produce a noise residue signal. The noise residue signal is converted to a power residue signal. The power residue signal is correlated with a Pseudo Random Bit Sequences (PRBS) sequence used to generate the written signal to produce a deconvolved signal. The deconvolved signal is accumulated.

Abstract: An apparatus for providing dynamic equalizer optimization is disclosed. The present invention solves the above-described problems by providing equalizer coefficient updates that converge towards the same solution as the direct method without having to first write a known pattern to the disk or requiring any prior knowledge of the data already written on the disk. The adaptive cosine function may be used to modify only a DFIR tap set, only the j and k parameters of a cosine equalizer or to modify both the tap set for a DFIR filter and the j and k parameters of the cosine equalizer. Another algorithm, such as the LMS algorithm, may be used to modify parameters not modified by the cosine algorithm.

Abstract: An apparatus for providing data dependent detection in a data read channel is disclosed. Parameters in a read channel are dynamically adjusted according to data dependent noise. For example, a comparison in an add-compare-select (ACS) unit of a Viterbi decoder may be adjusted or offset terms in error event filters may be biased to choose a Viterbi sequence with more transitions or to compensate for polarity dependent noise.

Abstract: A method and apparatus for data coding for high-density recording channels exhibiting low frequency contents is disclosed. Coding is used that satisfies both Running Digital Sum (RDS) and Maximum Transition Run (MTR) properties, which are desirable for achieving high-density recording for recording channels exhibiting low frequency components such as perpendicular magnetic recording channel.

Abstract: Described is a modulation encoder having a finite state machine for converting input bits into output bits in which the number of alternating output bits is limited to j+1 where j is a predefined maximum number of transitions in the output bits, and in which the number of like output bits is limited to k+1 where k is a predefined maximum number of non-transitions in the output bits. The modulation encoder may be employed in encoding apparatus for converting an input bit stream into an output bit stream. Such apparatus may comprise partitioning logic for partitioning the input bit stream into a first group of bits and a second group of bits. A plurality of the aforementioned modulation encoders may be connected to the partitioning logic for converting the first group of bits into coded output bits. Combining logic may be connected to the or each modulation encoder and the partitioning logic for combining the coded output bits and the second group of bits to generate the output bit stream.

Abstract: Described is a modulation encoder having a finite state machine for converting input bits into output bits in which the number of alternating output bits is limited to j+1 where j is a predefined maximum number of transitions in the output bits, and in which the number of like output bits is limited to k+1 where k is a predefined maximum number of non-transitions in the output bits. The modulation encoder may be employed in encoding apparatus for converting an input bit stream into an output bit stream. Such apparatus may comprise partitioning logic for partitioning the input bit stream into a first group of bits and a second group of bits. A plurality of the aforementioned modulation encoders may be connected to the partitioning logic for converting the first group of bits into coded output bits. Combining logic may be connected to the or each modulation encoder and the partitioning logic for combining the coded output bits and the second group of bits to generate the output bit stream.

Abstract: Maximum transition run encoding of a succession of M-bit data words to produce a succession of N-bit code words, where N→−M, for supply to a magnetic recording channel is described. Each M-bit data word is encoded in accordance with an MTR coding scheme to produce a G-bit word, where N→−G→M, such that the maximum number of consecutive bits of a first value, generally bits of value “1”, in a succession of the G-bit words is limited to a first predetermined value j1. The G-bit word is then encoded to produce an N-bit word in accordance with a second coding scheme.

Abstract: In a maximum likelihood sequence detector for symbol sequences which were equalized in a PR4 equalizer, noise prediction means (35) are provided including infinite impulse response (IIR) filtering, which have noise-whitening capabilities and are imbedded into the maximum likelihood detection process. The resulting INPML detector (10) can be implemented in digital or analog circuit technology. In addition, a DC-notch filter (44a) and a stochastic gradient procedure can be provided for DC offset compensation and for MR head or signal asymmetry compensation.

Abstract: A method and apparatus for identifying the start of a data field using a fault tolerant sync word with 16/17 rate coding is enclosed. The invention provides a word sync field that uses a 16/17 byte pattern that is repeated. The format of the word sync allows the proper identification of the start of the data even if only certain portions of the word sync are recovered. An encoded data block includes a sync field for providing proper timing for bit synchronization and a word sync field following the sync field, the word sync field being written with a predetermined phase relative to the sync field to identify a start of a data field. The word sync field comprises N word sync patterns, each word sync pattern comprising two subpatterns, wherein the phase relationship of the word sync field and the sync field enables identification of the start of the data field by identifying any N subpatterns.

Abstract: A method and apparatus for encoding a plurality of successive m-bit binary data words to produce a plurality of successive of n-bit binary code words, where n and m are positive integers and n is greater than m, for supply to a magnetic recording channel. Each m-bit binary data word is partitioned into a plurality of blocks of bits, and at least one said blocks of bits in each m-bit binary data word is encoded in accordance with a finite-state coding scheme to produce a plurality of successive n-bit binary code words. At least one stage of violation correction which transforms the plurality of successive n-bit binary code words. Violation correction includes detecting the occurrence of any of a plurality of prohibited bit patterns at one or more predetermined locations within each n-bit binary coded word, and replacing any prohibited bit pattern so detected by a corresponding substitute bit pattern.

Abstract: A method and apparatus for maximum likelihood detection of a sequential stream of binary bits. 2N binary states (N≧2) are projected onto a trellis at a sequence of times. Two branches to each binary state at time Ti+1 from a closest previous time Ti are identified (i≧N). There are 2N+1 such branches between Ti and Ti+1. A state metric for each of the 2N binary states at Ti and a branch metric for each of the 2N+1 branches between Ti and Ti+1 are provided. An illegal branch and a legal branch to a state S1 at time Ti+1 are so designated. A state metric is computed at each of the 2N binary states at time Ti+1 as a function of: the state metrics at Ti, the branch metrics between Ti and Ti+1, and the 2 branches to state S1.

Abstract: A combined read and write VCO for data channels is disclosed. The combined read and write VCO for data channels shares a common loop capacitor while providing optimal read and write VCO loop responses, and allows the VCO to relock to the write timebase after a read very quickly while maintaining an accurate timebase. The combined read and write VCO includes an oscillator providing an output signal having a frequency that varies proportionately to an oscillator input signal and an adjustable voltage source, the adjustable voltage source having a first configuration for a write mode and a second configuration for a read mode, and the adjustable voltage source providing the oscillator input signal to the oscillator in response to receiving an input current signal. The adjustable voltage source includes a first and second capacitor coupled in series and a switch coupled across the second capacitor, the switch being open to provide the first configuration and closed to provide the second configuration.

Abstract: A method and apparatus for automating the convergence of tap weights in an equalizer for a data channel is disclosed. The automated equalization method is contained within the channel and obtains a temporary copy of each of a plurality of current tap weights from a current tap weight memory, determines a direction for modifying the temporary copy of each of the plurality of current tap weights, constrains the modifications to the temporary copy of each of the plurality of current tap weights to produce adjusted tap weights and at the end of a read operation, stores the adjusted tap weights to the current tap weight memory for use during a next read operation.

Abstract: A noise-predictive data detection method and apparatus are provided for enhanced noise-predictive maximum-likelihood (NPML) data detection in a direct access storage device. A data signal from a data channel in the direct access storage device is applied to a maximum-likelihood detector that provides an estimated sequence signal. A noise bleacher filter having a frequency response of (1+.alpha.D)/1-.beta.D.sup.2) receives a combined estimated sequence signal and data signal and provides a noise filtered signal. A matching and error event filter receives the noise filtered signal and provides an error event filtered signal. An error correction unit receives the estimated sequence signal from the maximum-likelihood detector and receives the error event filtered signal and provides an error corrected estimated sequence signal.

Abstract: A method and apparatus are provided for maximum-likelihood data detection in a partial-response (PR) data channel including a head and disk assembly providing an analog signal coupled to an analog to digital converter (ADC) providing digital samples. A plurality of digital samples are received from the ADC. The received digital samples are applied to a selected first filter and a selected second filter. The first filtered digital samples are applied to a first data detector, and the second filtered digital samples are applied to a second data detector. A predetermined parameter is identified, and at least one of the first and second data detectors is selected responsive to the identified predetermined parameter.

Abstract: Apparatus and method for asynchronous gain adjustment are provided for data detection in a partial-response maximum-likelihood (PRML) data channel. The PRML data channel includes an analog to digital converter (ADC) having a normal operating range and a filter, gain and timing control coupled to the ADC. A plurality of samples are detected from the ADC. Each of the detected samples are sequentially compared with predetermined threshold values. The predetermined threshold values include a zero value, and a minimum value and a maximum value of the normal operating range of the ADC. An absolute value of each of the detected samples are sequentially compared with a forth predetermined threshold value. A gain adjustment correction value is determined utilizing the sequentially compared values.