Abstract: An alignment mark to be used in conjunction with e-beam imaging to identify specific feature locations on a chip including a unique “L” shaped pattern of geometric features, which is easily detected by the recognition system of e-beam imaging equipment, and is located in close proximity to the specific circuit features under investigation at each level to be inspected. The requirements for an alignment mark design which is recognizable by state-of-the-art e-beam imaging systems are enumerated, as well as the methodology for application. The alignment marks which are included at each critical step add no cost to wafer processing, and any design cost is easily overcome by reduction in process development time by using defect learning.

Abstract: The present invention provides an electroplating process and a method for manufacturing an integrated circuit. The electroplating process includes, among other steps, placing a substrate 290 in an enclosure 200 being substantially devoid of unwanted contaminants and forming a material layer 310 over the substrate 290 within the enclosure 200, the enclosure 200 still being substantially devoid of the unwanted contaminants. The electroplating process further includes forming a thin layer of oxide 410 over the material layer 310 within the enclosure 200, the enclosure 200 still being substantially devoid of the unwanted contaminants during the forming the thin layer of oxide 410.

Abstract: An in-situ particle monitor in an exhaust controls a particle sampler so that when a predetermined particle threshold is detected, the particle sampler is caused to gather samples from the exhaust in real-time. Electrical control signals are monitored to correlate variations in the signals with particle excursions for both analysis and sample collection triggering.

Abstract: Wafer order is randomized in-situ by use of a separate wafer staging area and randomly shuffling wafers to and from this staging area to shuffle the processing order of the wafer lot. Positional data is captured for each wafer at both the send and receive ends of the process.

Abstract: A subset test module and associated methodology for utilizing the same are disclosed that facilitate identification of process drift in semiconductor fabrication processing. A test wafer having a plurality of die formed thereon has a plurality of test modules formed within the die. The plurality of test modules are substantially the same from die to die, and the respective modules similarly include a plurality of test structures that are substantially the same from module to module. Corresponding test structures within respective modules on different die are inspected and compared to one another to find structures that are sensitive to process drift. One or more structures that experience differences from module to module on different die are utilized to develop one or more test modules that can be selectively located within production wafers and monitored to determine whether process drift and/or one or more other aberrant processing conditions are occurring.

Abstract: Wafer order is randomized in-situ by use of a separate wafer staging area and randomly shuffling wafers to and from this staging area to shuffle the processing order of the wafer lot. Positional data is captured for each wafer at both the send and receive ends of the process.

Abstract: A photolithography system includes a photolithography tool 32 that includes a stage upon which a semiconductor wafer is mounted. The tool is operable to move the stage to automatically focus a pre-determined image on a surface of the semiconductor wafer. The tool is further operable to log movements of the stage. The system also includes an automation host computer 36 operable to poll the photolithography tool 32 to obtain data reflecting the logged movements of the stage. The automation host computer 36 is further operable to analyze the data and compare the data to pre-determined error conditions. The host computer also takes a pre-determined action, including sending an electronic mail message to the personal computers 38 of relevant line personnel, in the event the data meets the pre-determined error conditions.

Abstract: A system (25) for detecting defects in a semiconductor wafer (10), such defects including voids (V) present in metal conductors (2, 4) and plugs (7), is disclosed. An x-ray source (20) irradiates the wafer (10) through a first aperture array (24) having openings (26); a second aperture array (28) is located on the opposite side of the wafer (10) from the source (20), and has openings (30) that are aligned and registered with the openings (26) in the first aperture array (24). An array of x-ray detectors (31) is located adjacent to the second aperture array (28), with each detector (31) associated with one of the openings (30) of the second aperture array (28). The detectors (31) communicate signals regarding the magnitude of x-ray energy that is transmitted through wafer (10) at locations defined by the openings (26, 30) through aperture arrays (24, 28), to an analysis computer (34). A wafer translation system (32) indexes or otherwise moves the wafer (10) between the aperture arrays (24, 28).

Abstract: The present invention provides, in one embodiment, a method (100) of manufacturing a semiconductor device. A conventionally formed reticle is positioned over a resist located on a substrate (110). A radiation path through the reticle and a window assembly located between a radiation source and resist (120), is considered. It is determined whether or not the radiation would expose a predefined blocking area of the resist within the exposure zone (130). If the radiation would expose a blocking area, then the window assembly is configured to prevent radiation from exposing the blocking area in the exposure zone (140). Other embodiments include a window assembly (300) and system (400) to facilitate manufacturing of the semiconductor device according to the method (100).

Abstract: A subset test module and associated methodology for utilizing the same are disclosed that facilitate identification of process drift in semiconductor fabrication processing. A test wafer having a plurality of die formed thereon has a plurality of test modules formed within the die. The plurality of test modules are substantially the same from die to die, and the respective modules similarly include a plurality of test structures that are substantially the same from module to module. Corresponding test structures within respective modules on different die are inspected and compared to one another to find structures that are sensitive to process drift. One or more structures that experience differences from module to module on different die are utilized to develop one or more test modules that can be selectively located within production wafers and monitored to determine whether process drift and/or one or more other aberrant processing conditions are occurring.

Abstract: Wafer order is randomized in-situ by use of a separate wafer staging area and randomly shuffling wafers to and from this staging area to shuffle the processing order of the wafer lot. Positional data is captured for each wafer at both the send and receive ends of the process.

Abstract: Wafer order is randomized in-situ by use of a separate wafer staging area and randomly shuffling wafers to and from this staging area to shuffle the processing order of the wafer lot. Positional data is captured for each wafer at both the send and receive ends of the process.

Abstract: The marking of identification and orientation information along the edge (E) of a semiconductor wafer (20, 20′) is disclosed. The information may be marked by way of laser marking at one or more locations (10) along a flat portion (14) or bevel (12t, 12b) of the edge (E) of the wafer (20, 20′). The wafer marking (10) may be encoded, for example by way of a 2-D bar code. A system (30) for reading the identification information from wafers (20, 20′) in a carrier (32) is also disclosed. The system (30) includes a sensor (36) for sensing reflected light from the wafer markings (10) along the wafer edge (E), and for decoding identification and orientation therefrom. A motor (38), under the control of feedback (RFB) from the sensor (36), rotates the wafers (20, 20′) by way of a roller (39) until the wafer marking (10) is in view by the sensor (36). A processing system (40), which includes a rotatable chuck (41) upon which the wafer (20, 20′) is placed, is also disclosed.

Abstract: An alignment mark to be used in conjunction with e-beam imaging to identify specific feature locations on a chip including a unique “L” shaped pattern of geometric features, which is easily detected by the recognition system of e-beam imaging equipment, and is located in close proximity to the specific circuit features under investigation at each level to be inspected. The requirements for an alignment mark design which is recognizable by state-of-the-art e-beam imaging systems are enumerated, as well as the methodology for application. The alignment marks which are included at each critical step add no cost to wafer processing, and any design cost is easily overcome by reduction in process development time by using defect learning.

Abstract: The marking of identification and orientation information along the edge (E) of a semiconductor wafer (20, 20′) is disclosed. The information may be marked by way of laser marking at one or more locations (10) along a flat portion (14) or bevel (12t, 12b) of the edge (E) of the wafer (20, 20′). The wafer marking (10) may be encoded, for example by way of a 2-D bar code. A system (30) for reading the identification information from wafers (20, 20′) in a carrier (32) is also disclosed. The system (30) includes a sensor (36) for sensing reflected light from the wafer markings (10) along the wafer edge (E), and for decoding identification and orientation therefrom. A motor (38), under the control of feedback (RFB) from the sensor (36), rotates the wafers (20, 20′) by way of a roller (39) until the wafer marking (10) is in view by the sensor (36). A processing system (40), which includes a rotatable chuck (41) upon which the wafer (20, 20′) is placed, is also disclosed.

Abstract: A photolithography system includes a photolithography tool 32 that includes a stage upon which a semiconductor wafer is mounted. The tool is operable to move the stage to automatically focus a pre-determined image on a surface of the semiconductor wafer. The tool is further operable to log movements of the stage. The system also includes an automation host computer 36 operable to poll the photolithography tool 32 to obtain data reflecting the logged movements of the stage. The automation host computer 36 is further operable to analyze the data and compare the data to pre-determined error conditions. The host computer also takes a pre-determined action, including sending an electronic mail message to the personal computers 38 of relevant line personnel, in the event the data meets the pre-determined error conditions.

Abstract: An electroplating system is described which provides for the formation of a conductive layer on a workpiece. The current used to electroplate the workpiece is controlled by a controller. The rotation of the workpiece within a solution containing conductive material is controlled by a rotation controller. The current level and/or rotation of the workpiece is controlled in such a way that the non-uniform growth of large grains within the conductive film is minimized.

Abstract: Wafer order is randomized in-situ by use of a separate wafer staging area and randomly shuffling wafers to and from this staging area to shuffle the processing order of the wafer lot. Positional data is captured for each wafer at both the send and receive ends of the process.

Abstract: A photolithography system includes a photolithography tool 32 that includes a stage upon which a semiconductor wafer is mounted. The tool is operable to move the stage to automatically focus a pre-determined image on a surface of the semiconductor wafer. The tool is further operable to log movements of the stage. The system also includes an automation host computer 36 operable to poll the photolithography tool 32 to obtain data reflecting the logged movements of the stage. The automation host computer 36 is further operable to analyze the data and compare the data to pre-determined error conditions. The host computer also takes a pre-determined action, including sending an electronic mail message to the personal computers 38 of relevant line personnel, in the event the data meets the pre-determined error conditions.

Abstract: A method for rinsing a substrate held by a substrate holder in an electroplater includes positioning at least a first portion of the substrate holder and an electroplating bath in the electroplater relative to one another such that the substrate and the first portion of the substrate holder are removed from the electroplating bath. A retractable shutter in the electroplater is closed to where the closed retractable shutter is located between the first portion of the substrate holder and the electroplating bath as positioned. The substrate is rinsed with a solution wherein the closed retractable shutter prevents substantially all of the solution from entering into the electroplating bath.