Patents by Inventor Richard Leo Galbraith
Richard Leo Galbraith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230085085Abstract: Methods and apparatus are provided for controlling wireless signal transmissions, wherein problematic symbol patterns are relocated to an erasure region of a data packet prior to erasure encoding and transmission. Relocating the problematic symbol patterns is done so that, when the resulting erasure codeword is punctured and transmitted, the problematic patterns are not transmitted. Yet, those patterns can be restored by the decoder at the receiving device using an erasure decoder in accordance with erasure decoding techniques, e.g., punctured low-density parity-check (LDPC) decoding techniques. In this manner, problematic symbol patterns that may be corrupting during transmission due to noise are removed (punctured) prior to transmission, then restored by the decoder during decoding.Type: ApplicationFiled: September 14, 2021Publication date: March 16, 2023Inventors: Richard Leo Galbraith, Iouri Oboukhov, Jonas Andrew Goode
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Patent number: 11545999Abstract: A data storage system and method are provided for storing data in non-volatile memory devices. Binary data is received for storage in a non-volatile memory device. The binary data is converted into non-binary data comprising base-X values, where X is an integer greater than two. The non-binary data is encoded to generate a codeword and the codeword is written to a wordline of the non-volatile memory device.Type: GrantFiled: February 22, 2021Date of Patent: January 3, 2023Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Richard Leo Galbraith, Jonas Andrew Goode, Niranjay Ravindran
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Publication number: 20210319837Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.Type: ApplicationFiled: June 25, 2021Publication date: October 14, 2021Inventors: Richard David BARNDT, Aldo Giovanni COMETTI, Richard Leo GALBRAITH, Jonas Andrew GOODE, Niranjay RAVINDRAN, Anthony Dwayne WEATHERS
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Patent number: 11101006Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.Type: GrantFiled: July 6, 2020Date of Patent: August 24, 2021Assignee: Western Digital Technologies, Inc.Inventors: Richard David Barndt, Aldo Giovanni Cometti, Richard Leo Galbraith, Jonas Andrew Goode, Niranjay Ravindran, Anthony Dwayne Weathers
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Publication number: 20210175903Abstract: A data storage system and method are provided for storing data in non-volatile memory devices. Binary data is received for storage in a non-volatile memory device. The binary data is converted into non-binary data comprising base-X values, where X is an integer greater than two. The non-binary data is encoded to generate a codeword and the codeword is written to a wordline of the non-volatile memory device.Type: ApplicationFiled: February 22, 2021Publication date: June 10, 2021Inventors: Richard Leo GALBRAITH, Jonas Andrew GOODE, Niranjay RAVINDRAN
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Patent number: 10990295Abstract: The disclosure relates in some aspects to optimizing writes levels used for programming a non-volatile memory device. In some aspects, the disclosure relates to an algorithmic approach for adjusting write levels for a NAND flash device. For example, write level gradients may be iteratively generated based on memory cell bin distribution statistics relating to the number and direction of errors across bin boundaries.Type: GrantFiled: October 11, 2018Date of Patent: April 27, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Richard Leo Galbraith, Niranjay Ravindran, Jonas Andrew Goode
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Patent number: 10965321Abstract: A data storage system and method are provided for storing data in non-volatile memory devices. Binary data is received for storage in a non-volatile memory device. The binary data is converted into non-binary data comprising base-X values, where X is an integer greater than two. The non-binary data is encoded to generate a codeword and the codeword is written to a wordline of the non-volatile memory device.Type: GrantFiled: December 13, 2019Date of Patent: March 30, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Richard Leo Galbraith, Jonas Andrew Goode, Niranjay Ravindran
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Patent number: 10897271Abstract: The disclosure relates in some aspects to multi-dimensional quasi-cyclic (QC) low-density parity-check (LDPC) code generation. In one example, a controller of a data storage apparatus determines a plurality of dimensions for a code, the plurality of dimensions comprising a plurality of coprime numbers, generates distinct circulant rotation values based on at least a root of unity number and a prime number, assigns a different one of the distinct circulant rotation values to each of a plurality of circulant locations defined within the plurality of dimensions to generate the code, and encodes data using the code.Type: GrantFiled: October 4, 2018Date of Patent: January 19, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Richard Leo Galbraith, Iouri Oboukhov, Niranjay Ravindran
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Publication number: 20200335173Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.Type: ApplicationFiled: July 6, 2020Publication date: October 22, 2020Inventors: Richard David BARNDT, Aldo Giovanni COMETTI, Richard Leo GALBRAITH, Jonas Andrew GOODE, Niranjay RAVINDRAN, Anthony Dwayne WEATHERS
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Patent number: 10748628Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.Type: GrantFiled: March 14, 2019Date of Patent: August 18, 2020Assignee: Western Digital Technologies, Inc.Inventors: Richard David Barndt, Aldo Giovanni Cometti, Richard Leo Galbraith, Jonas Andrew Goode, Niranjay Ravindran, Anthony Dwayne Weathers
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Publication number: 20200115555Abstract: A data storage system and method are provided for storing data in non-volatile memory devices. Binary data is received for storage in a non-volatile memory device. The binary data is converted into non-binary data comprising base-X values, where X is an integer greater than two. The non-binary data is encoded to generate a codeword and the codeword is written to a wordline of the non-volatile memory device.Type: ApplicationFiled: December 13, 2019Publication date: April 16, 2020Inventors: Richard Leo GALBRAITH, Jonas Andrew GOODE, Niranjay RAVINDRAN
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Publication number: 20200112322Abstract: The disclosure relates in some aspects to multi-dimensional quasi-cyclic (QC) low-density parity-check (LDPC) code generation. In one example, a controller of a data storage apparatus determines a plurality of dimensions for a code, the plurality of dimensions comprising a plurality of coprime numbers, generates distinct circulant rotation values based on at least a root of unity number and a prime number, assigns a different one of the distinct circulant rotation values to each of a plurality of circulant locations defined within the plurality of dimensions to generate the code, and encodes data using the code.Type: ApplicationFiled: October 4, 2018Publication date: April 9, 2020Inventors: Richard Leo Galbraith, Iouri Oboukhov, Niranjay Ravindran
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Patent number: 10530391Abstract: A data storage system and method are provided for storing data in non-volatile memory devices. Binary data is received for storage in a non-volatile memory device. The binary data is converted into non-binary data comprising base-X values, where X is an integer greater than two. The non-binary data is encoded to generate a codeword and the codeword is written to a wordline of the non-volatile memory device.Type: GrantFiled: July 27, 2017Date of Patent: January 7, 2020Assignee: Western Digital Technologies, Inc.Inventors: Richard Leo Galbraith, Jonas Andrew Goode, Niranjay Ravindran
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Publication number: 20190384504Abstract: The disclosure relates in some aspects to optimizing writes levels used for programming a non-volatile memory device. In some aspects, the disclosure relates to an algorithmic approach for adjusting write levels for a NAND flash device. For example, write level gradients may be iteratively generated based on memory cell bin distribution statistics relating to the number and direction of errors across bin boundaries.Type: ApplicationFiled: October 11, 2018Publication date: December 19, 2019Inventors: Richard Leo Galbraith, Niranjay Ravindran, Jonas Andrew Goode
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Patent number: 10404290Abstract: A method and data storage system receives a confidence vector for a non-binary symbol value read from a memory cell of a non-volatile memory device, where the confidence vector includes a first plurality of confidence values and transforms the first plurality of confidence values into a first plurality of likelihood values using a forward tensor-product transform. A respective binary message passing decoding operation is performed with each of the first plurality of likelihood values to generate a second plurality of likelihood values, and the second plurality of likelihood values are transformed into a second plurality of confidence values of the confidence vector using a reverse tensor-product transform.Type: GrantFiled: July 31, 2017Date of Patent: September 3, 2019Assignee: Western Digital Technologies, Inc.Inventors: Richard Leo Galbraith, Niranjay Ravindran, Roger William Wood
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Publication number: 20190214101Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.Type: ApplicationFiled: March 14, 2019Publication date: July 11, 2019Inventors: Richard David Barndt, Aldo Giovanni Cometti, Richard Leo Galbraith, Jonas Andrew Goode, Niranjay Ravindran, Anthony Dwayne Weathers
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Patent number: 10236070Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.Type: GrantFiled: July 31, 2017Date of Patent: March 19, 2019Assignee: Western Digital Technologies, Inc.Inventors: Richard David Barndt, Aldo Giovanni Cometti, Richard Leo Galbraith, Jonas Andrew Goode, Niranjay Ravindran, Anthony Dwayne Weathers
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Publication number: 20180374550Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.Type: ApplicationFiled: July 31, 2017Publication date: December 27, 2018Inventors: Richard David BARNDT, Aldo Giovanni COMETTI, Richard Leo GALBRAITH, Jonas Andrew GOODE, Niranjay RAVINDRAN, Anthony Dwayne WEATHERS
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Patent number: 10008229Abstract: A method, apparatus, and system are provided for implementing track following using signal asymmetry metrics monitored during read back in hard disk drives (HDDs). Signal asymmetry metrics monitored during read back are used together with a position error signal (PES) to correct and guide the position of a read sensor with respect to a written track in the HDD.Type: GrantFiled: January 5, 2016Date of Patent: June 26, 2018Assignee: WESTERN DIGITAL TECHNOLOGIES, INCInventors: Richard Leo Galbraith, Weldon Mark Hanson, Mark A. Nichols, Alexander Taratorin, Roger William Wood
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Patent number: 9886979Abstract: A method, apparatus, and system are provided for implementing an enhanced modulation code for hard disk drives (HDDs). A modulation code directly uses Bit Error Rate (BER) information for different user patterns to construct a coded word minimizing possible error rate. The modulation code has a flexible code rate that simplifies code optimization relative to Coded Bit Density (CBD), signal to noise ratio (SNR) and noise color.Type: GrantFiled: December 30, 2016Date of Patent: February 6, 2018Assignee: Western Digital Technologies, Inc.Inventors: Richard Leo Galbraith, Weldon Mark Hanson, Iouri Oboukhov, Gary William Walker