Patents by Inventor Richard Leo Galbraith
Richard Leo Galbraith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120163074Abstract: A Flash memory system and a method for data management using the embodiments of the invention use special test cells with Early Degradation Detection (EDD) circuitry instead of using the actual user-data storage cells are described. The Flash memory test cells can be made to serve as a “canary in a coal mine” by being made more sensitive than the standard cells by using experimentally determined sensitive write VT and variable read VT. Techniques for early degradation detection (EDD) in Flash memories measure the dispersion of the threshold voltages (VT's), of a set (e.g. page) of NAND Flash memory cells during read operations. In an embodiment of the invention the time-to-completion (TTC) values for the read operation for the memory cells are used as a proxy for dispersion of the threshold voltages (VT's). A Dispersion Analyzer determines the dispersion of the set of TTC values.Type: ApplicationFiled: December 22, 2010Publication date: June 28, 2012Inventors: Luiz M. Franca-Neto, Richard Leo Galbraith, Travis Roger Oenning
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Patent number: 8209578Abstract: A system corrects errors in a bit stream. The system includes an encoder and a decoder. The encoder encodes the bit stream using a low density parity check code by inserting parity check bits into the bit stream to generate codewords. The decoder decodes the codewords using parity check equations that are based on the low density parity check code. The parity check bits may comprise no more than four percent of the bits in the codewords of the low density parity check code. The low density parity check code can have a minimum separation of at least 7 between any two ones in each row of a parity-check matrix that is based on the low density parity check code. The encoder and the decoder can be defined in hardware using logic circuits that are interconnected to implement a trellis based on the low density parity check code.Type: GrantFiled: March 11, 2008Date of Patent: June 26, 2012Assignee: Hitachi Global Storage Technologies Netherlands, B.V.Inventors: Richard Leo Galbraith, Bruce Alexander Wilson, Travis Roger Oenning, Mario Blaum, Ksenija Lakovic, Ivana Djurdjevic
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Patent number: 8166376Abstract: A system corrects errors in a codeword. The system includes a channel that sorts reliability numbers of symbols in the codeword to create an ordered list of candidate erasure locations. The system also includes a generalized minimum distance decoder that iteratively processes the ordered list of candidate erasure locations and at least two syndromes of the codeword using a single-shot key equation solver to generate an error locator polynomial and an error evaluator polynomial. The generalized minimum distance decoder processes the least reliable candidate erasure locations first within the ordered list of candidate erasure locations.Type: GrantFiled: April 8, 2008Date of Patent: April 24, 2012Assignee: Hitachi Global Storage Technologies Netherlands, B. V.Inventors: Martin Hassner, Travis Roger Oenning, Richard Leo Galbraith
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Patent number: 8037393Abstract: A detector generates a detected sequence, and a post processor generates probability values that indicate the likelihood of a plurality of error events in the detected sequence. The post processor partitions the values into first and second subsets. The post processor selects a first most likely value from the first subset of the values and a second most likely value from the second subset of the values. The post processor generates a bit reliability based on the first and the second most likely values.Type: GrantFiled: June 29, 2007Date of Patent: October 11, 2011Assignee: Hitachi Global Storage Technologies Netherlands, B.V.Inventors: Ivana Djurdjevic, Richard Leo Galbraith, Bruce Alexander Wilson, Yuan Xing Lee, Travis Roger Oenning, Mario Blaum, Ksenija Lakovic, Zongwang Li
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Patent number: 8037394Abstract: Techniques are provided that generate bit reliabilities for a detected sequence. A detector generates the detected sequence. According to one embodiment, a post-processor finds a first set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the first bit value, finds a second set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the second bit value, selects a first most likely combination of one or more events of the first set and a second most likely combination of one or more events of the second set, and generates a bit reliability based on the first and the second most likely values.Type: GrantFiled: June 29, 2007Date of Patent: October 11, 2011Assignee: Hitachi Global Storage Technologies Netherlands, B.V.Inventors: Ivana Djurdjevic, Bruce Alexander Wilson, Mario Blaum, Richard Leo Galbraith, Ksenija Lakovic, Yuan Xing Lee, Zongwang Li, Travis Roger Oenning
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Patent number: 7974037Abstract: A data storage device includes a first filter that generates a short DC equalization target in response to a read back signal generated from magnetic patterns that are recorded on a storage medium using perpendicular recording. The data storage device also includes a first detector that generates an output sequence in response to the short DC equalization target. The data storage device also includes a high pass filter that attenuates DC components of the short DC equalization target and that passes low frequency components of the short DC equalization target above a cutoff frequency to generate a filtered signal. The data storage device also includes a second detector that processes the output sequence in response to the filtered signal.Type: GrantFiled: February 21, 2008Date of Patent: July 5, 2011Assignee: Hitachi Global Storage Technologies Netherlands, B.V.Inventors: Richard Leo Galbraith, Travis Roger Oenning
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Publication number: 20100235718Abstract: Two levels of error correction decoding are performed using first and second level decoders. A composite code formed by combining an inner component code and an outer component code can be used to decode the data and correct any errors. Performing two level decoding using a composite code allows the size of the inner parity block to be reduced to a single Reed-Solomon symbol while keeping a good code rate. The first level decoder generates soft information. The soft information can indicate a most likely error event for each possible syndrome value of the inner component code. The soft information can also include error metric values for each of the most likely error events. The second level decoder generates corrected syndrome values based on the soft information using the outer component code. The most likely trellis path that corresponds to the corrected syndrome values is then selected.Type: ApplicationFiled: May 25, 2010Publication date: September 16, 2010Applicant: Hitachi Global Storage Technologies Netherlands, B.V.Inventors: Shaohua Yang, Richard Leo Galbraith, Ksenija Lakovic, Yuan Xing Lee, Travis Oenning, Jongseung Park, Hideki Sawaguchi, Bruce A. Wilson
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Patent number: 7733591Abstract: The invention includes apparatus and methods that allow a data storage device perform an enhanced data recovery procedure (DRP) that includes obtaining a new digital sampling of the voltages for the failing unit of data by re-reading the analog signal and converting it to digital form using an analog-to-digital conversion (ADC) using a fixed phase clock signal. The data samples are re-interpolated using a programmable delay line. The digital values representing the voltages are stored a buffer so that the data can be processed repeatedly using varying parameters as part of the data recovery procedure. Optionally the samples stored in the buffer can be processed in the reverse direction (from end of sector to beginning of sector) without requiring modification of the standard Viterbi detector since it inherently works on data processed in either direction.Type: GrantFiled: December 18, 2006Date of Patent: June 8, 2010Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Kraig Bottemiller, Richard Leo Galbraith, Weldon Mark Hanson, Travis Roger Oenning, Michael Joseph Ross, Fuminori Sai
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Patent number: 7725800Abstract: Two levels of error correction decoding are performed using first and second level decoders. A composite code formed by combining an inner component code and an outer component code can be used to decode the data and correct any errors. Performing two level decoding using a composite code allows the size of the inner parity block to be reduced to a single Reed-Solomon symbol while keeping a good code rate. The first level decoder generates soft information. The soft information can indicate a most likely error event for each possible syndrome value of the inner component code. The soft information can also include error metric values for each of the most likely error events. The second level decoder generates corrected syndrome values based on the soft information using the outer component code. The most likely trellis path that corresponds to the corrected syndrome values is then selected.Type: GrantFiled: August 5, 2005Date of Patent: May 25, 2010Assignee: Hitachi Global Stroage Technologies Netherlands, B.V.Inventors: Shaohua Yang, Richard Leo Galbraith, Ksenija Lakovic, Yuan Xing Lee, Travis Oenning, Jongseung Park, Hideki Sawaguchi, Bruce A. Wilson
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Patent number: 7675703Abstract: A system and method accurately clocks write data to the discrete data blocks in a patterned media disk drive. The precise time intervals between successive timing marks in the data tracks are measured by a timing mark detector that counts the integer number of write clock cycles between successive timing marks and the fractional part of a write clock cycle by detecting the phase difference between a timing mark and a reference signal. The resulting timing error is output to a write clock compensator. The write clock is capable of generating equally spaced primary phases and phases intermediate the primary phases. The compensator includes a phase rotator that controls which write clock phase is selected for output. The value in a phase register of the compensator is used to control the phase rotator to advance or retard the write clock phase, and thus to adjust its frequency and phase so as to be synchronized for writing to the data blocks.Type: GrantFiled: June 8, 2007Date of Patent: March 9, 2010Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Thomas R. Albrecht, David Timothy Flynn, Richard Leo Galbraith, Michael Anthony Moser, Bruce Alexander Wilson, Xiao Z. Wu
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Publication number: 20090274028Abstract: Embodiments of the present invention relate to the detection of synchronization marks in data storage and retrieval. To detect a synchronization mark, embodiments of the present invention require both pattern matching and proper phase alignment, following a repeating synchronization field. According to one particular embodiment, proper phase alignment following a repeated four bit synchronization field, is utilized in conjunction with pattern matching, to identify a synchronization mark. By allowing a synchronization mark to be identified only with proper phase alignment at the earliest possible occurrence of the synchronization mark, accuracy of synchronization mark detection may be improved.Type: ApplicationFiled: April 30, 2008Publication date: November 5, 2009Inventors: Richard Leo Galbraith, Weldon Mark Hanson, Travis Roger Oenning, Todd Carter Truax
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Publication number: 20090274247Abstract: Embodiments of the present invention relate to the detection of synchronization marks in data storage and retrieval. According to one embodiment, synchronization marks are detected from the output of a matched filter, upstream of the Viterbi detector. This approach avoids the delay associated with the latency of the Viterbi output, thereby allowing time to align parity framing and to properly start the time-varying trellis. Certain embodiments disclose 34- and 20-bit primary synchronization marks located at the beginning of a data region. Other embodiments disclose 16-, 20-, and 24-bit embedded synchronization marks located within a data region.Type: ApplicationFiled: April 30, 2008Publication date: November 5, 2009Inventors: Richard Leo Galbraith, Weldon Mark Hanson, Travis Roger Oenning, Todd Carter Truax
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Publication number: 20090254796Abstract: A system corrects errors in a codeword. The system includes a channel that sorts reliability numbers of symbols in the codeword to create an ordered list of candidate erasure locations. The system also includes a generalized minimum distance decoder that iteratively processes the ordered list of candidate erasure locations and at least two syndromes of the codeword using a single-shot key equation solver to generate an error locator polynomial and an error evaluator polynomial. The generalized minimum distance decoder processes the least reliable candidate erasure locations first within the ordered list of candidate erasure locations.Type: ApplicationFiled: April 8, 2008Publication date: October 8, 2009Applicant: Hitachi Global Storage Technologies Netherlands, B.V.Inventors: Martin Hassner, Travis Roger Oenning, Richard Leo Galbraith
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Publication number: 20090235142Abstract: A system corrects errors in a bit stream. The system includes an encoder and a decoder. The encoder encodes the bit stream using a low density parity check code by inserting parity check bits into the bit stream to generate codewords. The decoder decodes the codewords using parity check equations that are based on the low density parity check code. The parity check bits may comprise no more than four percent of the bits in the codewords of the low density parity check code. The low density parity check code can have a minimum separation of at least 7 between any two ones in each row of a parity-check matrix that is based on the low density parity check code. The encoder and the decoder can be defined in hardware using logic circuits that are interconnected to implement a trellis based on the low density parity check code.Type: ApplicationFiled: March 11, 2008Publication date: September 17, 2009Applicant: Hitachi Global Storage Technologies Netherlands, B.V.Inventors: Richard Leo Galbraith, Bruce Alexander Wilson, Travis Roger Oenning, Mario Blaum, Ksenija Lakovic, Ivana Djurdjevic
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Patent number: 7590920Abstract: An error correction encoder inserts redundant parity information into a data stream to improve system reliability. The encoder can generate the redundant parity information using a composite code. Dummy bits are inserted into the data stream in locations reserved for parity information generated by subsequent encoding. The error correction code can have a uniform or a non-uniform span. The span corresponds to consecutive channel bits that are within a single block of a smaller parity code that is used to form a composite code. The span lengths can be variant across the whole codeword by inserting dummy bits in less than all of the spans.Type: GrantFiled: August 5, 2005Date of Patent: September 15, 2009Assignee: Hitachi Global Storage Technologies Netherlands, B.V.Inventors: Shaohua Yang, Mario Blaum, Richard Leo Galbraith, Ksenija Lakovic, Yuan Xing Lee, Travis Oenning, Jongseung Park, Hideki Sawaguchi
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Publication number: 20090213484Abstract: A data storage device includes a first filter that generates a short DC equalization target in response to a read back signal generated from magnetic patterns that are recorded on a storage medium using perpendicular recording. The data storage device also includes a first detector that generates an output sequence in response to the short DC equalization target. The data storage device also includes a high pass filter that attenuates DC components of the short DC equalization target and that passes low frequency components of the short DC equalization target above a cutoff frequency to generate a filtered signal. The data storage device also includes a second detector that processes the output sequence in response to the filtered signal.Type: ApplicationFiled: February 21, 2008Publication date: August 27, 2009Applicant: Hitachi Global Storage Technologies Netherlands, B.V.Inventors: Richard Leo Galbraith, Travis Roger Oenning
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Publication number: 20090006931Abstract: Techniques are provided that generate bit reliabilities for a detected sequence. A detector generates the detected sequence. According to one embodiment, a post-processor finds a first set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the first bit value, finds a second set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the second bit value, selects a first most likely combination of one or more events of the first set and a second most likely combination of one or more events of the second set, and generates a bit reliability based on the first and the second most likely values.Type: ApplicationFiled: June 29, 2007Publication date: January 1, 2009Applicant: Hitachi Global Storage Technologies Netherlands, B.V.Inventors: Ivana Djurdjevic, Bruce Alexander Wilson, Mario Blaum, Richard Leo Galbraith, Ksenija Lakovic, Yuan Xing Lee, Zongwang Li, Travis Roger Oenning
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Publication number: 20090006930Abstract: A detector generates a detected sequence, and a post processor generates probability values that indicate the likelihood of a plurality of error events in the detected sequence. The post processor partitions the values into first and second subsets. The post processor selects a first most likely value from the first subset of the values and a second most likely value from the second subset of the values. The post processor generates a bit reliability based on the first and the second most likely values.Type: ApplicationFiled: June 29, 2007Publication date: January 1, 2009Applicant: Hitachi Global Storage Technologies Netherlands, B.V.Inventors: Ivana Djurdjevic, Richard Leo Galbraith, Bruce Alexander Wilson, Yuan Xing Lee, Travis Roger Oenning, Mario Blaum, Ksenija Lakovic, Zongwang Li
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Publication number: 20080304173Abstract: A system and method accurately clocks write data to the discrete data blocks in a patterned media disk drive. The precise time intervals between successive timing marks in the data tracks are measured by a timing mark detector that counts the integer number of write clock cycles between successive timing marks and the fractional part of a write clock cycle by detecting the phase difference between a timing mark and a reference signal. The resulting timing error is output to a write clock compensator. The write clock is capable of generating equally spaced primary phases and phases intermediate the primary phases. The compensator includes a phase rotator that controls which write clock phase is selected for output. The value in a phase register of the compensator is used to control the phase rotator to advance or retard the write clock phase, and thus to adjust its frequency and phase so as to be synchronized for writing to the data blocks.Type: ApplicationFiled: June 8, 2007Publication date: December 11, 2008Applicant: HITACHI GLOBAL STORAGE TECHNOLOGIES NETHERLANDS B.V.Inventors: Thomas R. Albrecht, David Timothy Flynn, Richard Leo Galbraith, Michael Anthony Moser, Bruce Alexander Wilson, Xiao Z. Wu
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Publication number: 20080244359Abstract: Techniques are provided for iteratively decoding data recorded on a data storage device. An iterative decoder decodes the data using multiple decoding iterations to correct errors. In multiple iterations of the iterative decoder, a post processing block generates soft information, and a decoder applies a minimum sum decoding algorithm to a low density parity check (LDPC) code to generate extrinsic information based on the soft information and updated soft information.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Applicant: Hitachi Global Technologies Netherlands, B.V.Inventors: Zongwang Li, Yuan Xing Lee, Richard Leo Galbraith, Ivana Djurdjevic, Travis Roger Oenning