Abstract: Embodiments of the invention provide techniques for optimizing the detector target polynomials in read/write channels to achieve the best error rate performance in recording devices. In one embodiment, a method of obtaining a detector target polynomial of a read/write channel to achieve best error rate performance in a recording device comprises: providing an initial detector target for the read/write channel; measuring a noise autocorrelation of the read/write channel at the output of equalizer using channel hardware; computing a noise autocorrelation at the output of the 1st stage target based on the measured noise autocorrelation of the read/write channel at the output of equalizer; calculating optimal coefficients for the noise whitening filter; and obtaining the optimal detector target polynomial of the read/write channel using the calculated coefficients for noise whitening filter.

Abstract: The invention includes apparatus and methods that allow a data storage device perform an enhanced data recovery procedure (DRP) that includes obtaining a new digital sampling of the voltages for the failing unit of data by re-reading the analog signal and converting it to digital form using an analog-to-digital conversion (ADC) using a fixed phase clock signal. The data samples are re-interpolated using a programmable delay line. The digital values representing the voltages are stored a buffer so that the data can be processed repeatedly using varying parameters as part of the data recovery procedure. Optionally the samples stored in the buffer can be processed in the reverse direction (from end of sector to beginning of sector) without requiring modification of the standard Viterbi detector since it inherently works on data processed in either direction.

Abstract: A data recording medium has tracks with pseudo-noise (PN) sequences with good autocorrelation properties as servo information for controlling the position of the recording head. A first set of alternating tracks uses a leading pseudo-random binary sequence (PRBS), which is a PN sequence with good autocorrelation properties, and a following PRBS that is cyclically shifted from the leading PRBS. A second set of alternating tracks interleaved with the first set also has a leading PRBS and a following PRBS that is cyclically shifted from the leading PRBS, but the leading PRBS in each of the tracks in the second set is offset along-the-track from the leading PRBS in the tracks of the first set. The head positioning control system uses the leading PRBS to generate a servo timing mark (STM), the cyclic shift to generate track identification (TID), and the following PRBS from adjacent tracks to generate the head position error signal (PES).

Abstract: Non-uniform modulation encoding techniques are provided to prevent data from containing bit patterns that are prone to errors during read back. Modulation encoding is performed on a data stream to remove error prone bit patterns. Unconstrained data, such as error check parity, that is inserted into the modulated data stream may contain error prone bit patterns. Stricter modulation constraints are enforced on bits that are next to the unconstrained data, than on the remaining bits. By enforcing stricter modulation constraints on these bits, an entire data bit stream can have a desired modulation constraint.

Abstract: Techniques are provided for applying modulation constraints to data streams using a short block encoder. A short block encoder encodes a subset of the bits in a data stream. Then, the even and odd interleaves in a data stream are separated into two data paths. A first modulation encoder encodes the even interleave according to a first modulation constraint. A second modulation encoder encodes the odd interleave according to a second modulation constraint, which in general coincides with the modulation constraint for even interleave.

Abstract: Techniques are provided for applying modulation constraints to data by using periodically changing symbol mappings to replace certain prohibited error prone data patterns. Initially, user data in a first base is mapped to integers of a second base using a base conversion technique. The integers in the second base correspond to symbols. Subsequently, periodically changing symbol mappings are performed during which prohibited symbols generated during base conversion are mapped to permitted symbols. The periodically changing symbol mappings occur in multiple phases, and the prohibited symbols are different in each phase. The resulting data is processed by a precoder in some embodiments.

Abstract: A method and apparatus are provided for word synchronization with large coding distance and fault tolerance for a partial-response maximum-likelihood (PRML) data channel in a direct access storage device (DASD). A Viterbi detector receives equalized PR4 samples including a predefined word synchronization pattern. The Viterbi detector is a dedicated detector optimized for detecting the predefined word synchronization pattern. The Viterbi detector includes a two-state Viterbi trellis and a word synchronization detector for the two-state Viterbi trellis. The predefined word synchronization pattern includes only even length magnets. The predefined word synchronization pattern is a repetition code including pairs of ones and pairs of zeros and includes multiple pattern match sequences. The Viterbi detector is optimized with branches removed from the Viterbi trellis, thus increasing coding distance.

Abstract: A data recording system uses a recording medium in which the tracks have pseudo-noise (PN) sequences with good autocorrelation properties as servo information for controlling the position of the recording head. A first set of alternating tracks uses a leading pseudo-random binary sequence (PRBS), which is a PN sequence with good autocorrelation properties, and a following PRBS that is cyclically shifted from the leading PRBS. A second set of alternating tracks interleaved with the first set also has a leading PRBS and a following PRBS that is cyclically shifted from the leading PRBS, but the leading PRBS in each of the tracks in the second set is offset along-the-track from the leading PRBS in the tracks of the first set. The head positioning control system uses the leading PRBS to generate a servo timing mark (STM), the cyclic shift to generate track identification (TID), and the following PRBS from adjacent tracks to generate the head position error signal (PES).

Abstract: A method and apparatus are provided for implementing enhanced data channel performance using a read sample buffer in a direct access storage device (DASD). Disk data is read and stored in the read sample buffer. When a data recovery procedure (DRP) starts, the stored disk read data in the read sample buffer is detected. Error correction code (ECC) checking of the detected sample buffer disk data is performed to identify correctly recovered data. Using the disk read data stored in the read sample buffer enables data recovery without identification of a sync word. Also using the disk read data stored in the read sample buffer enables data recovery with changed channel data detection settings to recover the data. The read sample buffer can be used for accumulating read disk data from more than one read operation so that at least some channel noise is averaged out.

Abstract: A method and apparatus are provided for channel equalization with a digital finite impulse response (DFIR) filter using a pseudo random sequence. A readback signal of a pseudo random bit sequence is obtained. Samples are obtained from the readback signal of the pseudo random bit sequence. Tap gradients are calculated responsive to the obtained samples. The tap weights of the digital finite impulse response (FIR) filter are modified responsive to the calculated tap gradients. Dibit samples and error samples are obtained from the readback signal of the pseudo random bit sequence and applied to a tap gradients calculator. Tap gradients are calculated by a bitwise multiplier and accumulation tap gradient calculation circuit. An attenuation function attenuates the calculated tap gradients by a programmable attenuation value.

Abstract: A method and apparatus are provided for implementing soft-input soft-output iterative detectors/decoders. Soft-input information is added directly to incoming channel samples. Input signals comprising the received incoming channel samples with the added soft-input information are detected using a detector trellis. Branch metric terms are transformed to shift all time varying terms with the added soft-input information and some constant terms after an add compare select (ACS) unit. The shifted time varying terms with the added soft-input information and the shifted constant terms are added directly to state metric terms. The soft-input information is added directly to incoming channel samples and the computation of branch metrics is not affected. This allows optimization of a dual-max detector and soft-input soft-output Viterbi detector architectures to minimize hardware complexity and power consumption.

Abstract: A method for low-density parity-check (LDPC) encoding of data comprises defining a first M×N parity check matrix; generating, based on the first parity check matrix, a second parity check matrix having an M×M triangular sub-matrix; and, mapping the data into an LDPC code word based on the second parity check matrix. The method is particularly useful for data communications applications, but may also be employed in other applications such as, for example, data storage.

Abstract: Methods and apparatus for enhanced timing loop are provided for a partial-response maximum-likelihood (PRML) data channel in a direct access storage device (DASD). An acquisition timing circuit for generating an acquisition timing signal includes a plurality of compare functions for receiving and comparing consecutive input signal samples on an interleave with a threshold value. The acquisition timing circuit includes a majority rule voting function coupled to the plurality of compare functions for selecting a timing interleave. Tracking timing circuitry for generating a timing error signal during a read operation includes a channel data detector. The channel data detector receives disk signal input samples and includes a multiple-state path memory. The tracking timing circuit includes a low latency detector receiving disk signal input samples. A selector function is coupled to an output of the low latency detector and is coupled to the multiple-state path memory for selecting a state.

Abstract: A multi-pole electric pulse generator contains poles having a pseudo-random distribution. Preferably, poles are equally sized and spaced, and polarity corresponds to a pseudo-noise binary sequence, which is specifically a primitive polynomial m-sequence. At one point in the rotor's revolution, all rotor poles are aligned with corresponding stator poles to provide maximum net magnetic flux through the armature windings. At all other rotor positions, the poles are misaligned so that the net flux through the armature windings is small. In operation, rotation through the misaligned rotor positions produces essentially no flux change so that no electric power is generated. When the rotor reaches the aligned position, there is a sudden, large flux change which generates a high-energy electric pulse. The exemplary application is for generating an ignition spark of an internal combustion engine.

Abstract: An unconstrained equalization method and apparatus with gain and timing bias to control runaway are provided for a direct access storage device (DASD) data channel. A direction for moving each of a plurality of tap weights of a finite impulse response (FIR) filter is calculated. New tap weights are determined for each of a plurality of tap weights in the direction. A gain of the FIR filter for the new tap weights is compared with a set threshold gain value. A polarity of a gain bias is set to adjust a gain of a gain loop of the data channel by a preselected amount responsive to the compared gain and set threshold gain values, A phase lag of the FIR filter for the new tap weights is compared with a set threshold phase lag value. A polarity of a timing bias is set to adjust a phase lag of a timing loop of the data channel by a preselected amount responsive to the compared phase lag and set threshold phase lag values.

Abstract: A multi-pole electric pulse generator contains poles having a pseudo-random distribution. Preferably, poles are equally sized and spaced, and polarity corresponds to a pseudo-noise binary sequence, which is specifically a primitive polynomial m-sequence. At one point in the rotor's revolution, all rotor poles are aligned with corresponding stator poles to provide maximum net magnetic flux through the armature windings. At all other rotor positions, the poles are misaligned so that the net flux through the armature windings is small. In operation, rotation through the misaligned rotor positions produces essentially no flux change so that no electric power is generated. When the rotor reaches the aligned position, there is a sudden, large flux change which generates a high-energy electric pulse. The exemplary application is for generating an ignition spark of an internal combustion engine.

Abstract: A method and apparatus are provided for implementing enhanced data channel performance using a read sample buffer in a direct access storage device (DASD). Disk data is read and stored in the read sample buffer. When a data recovery procedure (DRP) starts, the stored disk read data in the read sample buffer is detected. Error correction code (ECC) checking of the detected sample buffer disk data is performed to identify correctly recovered data. Using the disk read data stored in the read sample buffer enables data recovery without identification of a sync word. Also using the disk read data stored in the read sample buffer enables data recovery with changed channel data detection settings to recover the data. The read sample buffer can be used for accumulating read disk data from more than one read operation so that at least some channel noise is averaged out.

Abstract: A method and apparatus are provided for thermal asperity recovery for word sync detection in data channels. A word sync field contains a plurality of word sync patterns. A word sync detector receives a read signal of the word sync field. The word sync detector identifies a first subset of the plurality of word sync patterns and starts a customer data read. When the word sync detector fails to identify the first subset of the plurality of word sync patterns, the read signal of the word sync field is received again. Then the word sync detector identifies a second predefined subset of the plurality of word sync patterns and starts a customer data read. A single word sync field is used instead of the conventional dual word sync fields required for each sector. The second predefined subset of the plurality of word sync patterns is smaller than the first subset. For example, when the first subset is defined as 4 of 8, the second predefined subset is 2 of 8.

Abstract: A method for low-density parity-check (LDPC) encoding of data comprises defining a first M×N parity check matrix; generating, based on the first parity check matrix, a second parity check matrix having an M×M triangular sub-matrix; and, mapping the data into an LDPC code word based on the second parity check matrix. The method is particularly useful for data communications applications, but may also be employed in other applications such as, for example, data storage.

Abstract: A method and apparatus are provided for channel equalization with a digital finite impulse response (DFIR) filter using a pseudo random sequence. A readback signal of a pseudo random bit sequence is obtained. Samples are obtained from the readback signal of the pseudo random bit sequence. Tap gradients are calculated responsive to the obtained samples. The tap weights of the digital finite impulse response (FIR) filter are modified responsive to the calculated tap gradients. Dibit samples and error samples are obtained from the readback signal of the pseudo random bit sequence and applied to a tap gradients calculator. Tap gradients are calculated by a bitwise multiplier and accumulation tap gradient calculation circuit. An attenuation function attenuates the calculated tap gradients by a programmable attenuation value.