Abstract: A method and apparatus are provided for word synchronization with large coding distance and fault tolerance for a partial-response maximum-likelihood (PRML) data channel in a direct access storage device (DASD). A Viterbi detector receives equalized PR4 samples including a predefined word synchronization pattern. The Viterbi detector is a dedicated detector optimized for detecting the predefined word synchronization pattern. The Viterbi detector includes a two-state Viterbi trellis and a word synchronization detector for the two-state Viterbi trellis. The predefined word synchronization pattern includes only even length magnets. The predefined word synchronization pattern is a repetition code including pairs of ones and pairs of zeros and includes multiple pattern match sequences. The Viterbi detector is optimized with branches removed from the Viterbi trellis, thus increasing coding distance.

Abstract: A method and apparatus are provided for implementing soft-input soft-output iterative detectors/decoders. Soft-input information is added directly to incoming channel samples. Input signals comprising the received incoming channel samples with the added soft-input information are detected using a detector trellis. Branch metric terms are transformed to shift all time varying terms with the added soft-input information and some constant terms after an add compare select (ACS) unit. The shifted time varying terms with the added soft-input information and the shifted constant terms are added directly to state metric terms. The soft-input information is added directly to incoming channel samples and the computation of branch metrics is not affected. This allows optimization of a dual-max detector and soft-input soft-output Viterbi detector architectures to minimize hardware complexity and power consumption.

Abstract: A method for use in connection with any kind of detector that receives an input signal via a partial-response channel and which provides a detector output signal and a merge-bit signal. According to the present scheme, the colored noise of the input signal is whitened in order to provide a filtered signal. The filtered signal is filtered to provide a first output signal using a first matched filter and a second output signal using a second matched filter. The merge-bit signal is used to adjust the first matched filter to match a first most likely error event and to adjust the second matched filter to match a second most likely error event. It is then determined whether said first likely error event or said second likely error event is the most likely error event, and the actual errors of detector output signal are corrected using said most likely error event.

Abstract: Methods and apparatus for enhanced timing loop are provided for a partial-response maximum-likelihood (PRML) data channel in a direct access storage device (DASD). An acquisition timing circuit for generating an acquisition timing signal includes a plurality of compare functions for receiving and comparing consecutive input signal samples on an interleave with a threshold value. The acquisition timing circuit includes a majority rule voting function coupled to the plurality of compare functions for selecting a timing interleave. Tracking timing circuitry for generating a timing error signal during a read operation includes a channel data detector. The channel data detector receives disk signal input samples and includes a multiple-state path memory. The tracking timing circuit includes a low latency detector receiving disk signal input samples. A selector function is coupled to an output of the low latency detector and is coupled to the multiple-state path memory for selecting a state.

Abstract: Methods and apparatus are provided for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals using both partial matched filter and matched filter metrics. In the method of the invention, branch metric terms are transformed to shift all time varying terms and some constant terms after an add compare select (ACS) unit. The total number of non-zero constants on trellis branches is minimized. The shifted time varying terms and the shifted constant terms are added directly to state metric terms. The time varying terms are expressed as outputs Zn of a partial matched filter or as outputs Wn of a matched filter. For a given generalized partial response target, the time-invariance property of the Viterbi detector enables identifying the minimum number of non-zero constants on trellis branches without resorting to heuristics.

Abstract: Apparatus is provided for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals including two-way add/compare/select for improved channel speed. The two-way add/compare/select includes a two-way compare for comparing first and second state metric input values and a pair of two-way adds in parallel with the two-way compare for respectively adding the first and second state metric input values with a second input value. The second input value includes a time varying term or a constant term. The time varying terms are expressed as outputs Zn of a partial matched filter or as outputs Wn of a matched filter. A multiplexer is coupled to the pair of two-way adds, the multiplexer receiving a selectable input controlled by the two-way compare. A pair of shifts coupled between the pair of two-way adds and the multiplexer receive a shift control input for providing metric bounding to avoid underflow.

Abstract: A method and apparatus are provided for detecting surface defects in a direct access storage device. Disk data readback sample values are converted to gain error values based upon an identified difference from predefined ideal data values. An error signal accumulator accumulates a summed value of error signals for a current sample and a predetermined number of past samples. Each sequential accumulator summed value is compared with a predetermined threshold value. An error output is generated responsive to each sequential accumulator summed value greater than or equal to the predetermined threshold value, the error output identifying the disk surface defect.

Abstract: The invention is family of noise predictive maximum liklihood (NPML) symbol detectors that are particularly useful in direct access storage devices. Various embodiments representative of the family of detectors are described. In general, the NPML detectors include a sequence detector with imbedded feedback which may be preceded by a filter, e.g., a prediction error filter. The sequence of detectors, which may be Viterbi detectors, have an imbedded filter whose coefficients are determined by the convolution of the partial response (PR) or generalized PR function with the predictor coefficients and do not require multiplications and, thus, allows a simple RAM look-up for intersymbol-interference ISI cancelation. In one class of embodiments, the NPML detector comprises a prediction error filter of length N, cascaded with a sequence detector having 2.sup.

Abstract: A phase locked loop unlock detector is provided for a data detection channel in a direct access storage device (DASD). The phase locked loop unlock detector includes a counter for generating a threshold reference relative to a reference signal. An unlock window generator is coupled to the counter for generating an unlock window signal. An unlock error detector is coupled to the unlock window generator for comparing a variable frequency signal with the unlock window signal.

Abstract: Methods and apparatus are provided for detecting servo information in a direct access storage device. A plurality of data symbols are read from a disk to produce a readback signal. Each data symbol and each sequence of data symbols contains servo identification information. A correlation filter provides a matched filter function of an expected readback signal of the plurality of data symbols to produce a correlated readback signal. A threshold detector is coupled to the correlation filter for identifying a threshold signal representative of the data symbol. A data separator responsive to the threshold detector windows the threshold signal and provides clock and data signals. The data separator includes a digital variable frequency oscillator (VFO) which optimally centers incoming servo information from the disk in a timing window and provides standard clocked data for a servo processor. The threshold detector has a variable threshold voltage that is programmed using a trim digital-to-analog converter (DAC).

Abstract: A method and apparatus are provided for data detection for a partial-response maximum-likelihood (PRML) data detection channel in a direct access storage device. A class-IV partial response (PR4) signal is applied to a PR4 Viterbi detector to provide a PR4 Viterbi output and is applied to a first matching delay circuit to provide a delayed PR4 signal. The PR4 Viterbi output is subtracted from the delayed PR4 signal and a resulting signal is applied to a first filter having a frequency response of 1/(1-.alpha.D.sup.2). The filtered output signal is applied to a second filter providing a second filtered output signal. The PR4 Viterbi output is applied to a second matching delay circuit to provide a delayed PR4 Viterbi output signal. The delayed PR4 Viterbi output is corrected responsive to the second filtered output signal. The first filter is an infinite impulse response (IIR) filter and the filtered output signal represents whitened noise and modified PRML error events.

Abstract: A data encoding method and apparatus are provided for implementing a predefined rate code, such as a 16/17 rate code for a data detection channel in a direct access storage device. A binary data stream is received and sequential symbols of the received binary data stream are identified. Sequential alternate symbols of the binary data stream are encoded into first codewords. Sequential alternate other symbols are encoded into second codewords. The alternating first and second codewords are sequentially combined. For a rate 16/17 rate code, the first codewords include 9-bit codewords and the second codewords include 8-bit codewords. The second 8-bit codewords are either raw symbols of the received binary data stream or remapped symbols of the received binary data stream. All likely error events are limited to within three consecutive bytes in a user data stream with a 16/17 rate code of the preferred embodiment.

Abstract: A method and apparatus are provided for gain adjustment of a signal. A plurality of comparators compare the signal with a plurality of threshold values. An envelope detector coupled to the comparator includes a peak capture function for detecting the amplitude of the signal and a polarity memory for detecting polarity of the signal. A gain control function for setting a gain correction value is responsive to the peak capture function and the polarity memory. Features of the signal gain adjustment method and apparatus of the invention include an intelligent hold of the gain control over both thermal asperities and null gaps in the signal.