Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a first transistor having a first active area, and a second transistor having a second active area. A top surface of the first active area is elevated or recessed with respect to a top surface of the second active area, or a top surface of the first active area is elevated or recessed with respect to a top surface of at least portions of an isolation region proximate the first transistor.

Abstract: A method of making a semiconductor device is disclosed. An upper surface of a semiconductor body is amorphized and a liner is formed over the amorphized upper surface. The upper surface can then be annealed. A transistor is formed at the upper surface.

Abstract: Semiconductor devices, capacitors, and methods of manufacture thereof are disclosed. In one embodiment, a method of fabricating a capacitor includes forming a first material over a workpiece, and patterning the first material, forming a first capacitor plate in a first region of the workpiece and forming a first element in a second region of the workpiece. A second material is formed over the workpiece and over the patterned first material. The second material is patterned, forming a capacitor dielectric and a second capacitor plate in the first region of the workpiece over the first capacitor plate and forming a second element in a third region of the workpiece.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a first transistor having a first active area, and a second transistor having a second active area. A top surface of the first active area is elevated or recessed with respect to a top surface of the second active area, or a top surface of the first active area is elevated or recessed with respect to a top surface of at least portions of an isolation region proximate the first transistor.

Abstract: Method of producing a semiconductor device, comprising: a) providing a semiconductor substrate, b) making a first amorphous layer in a top layer of the semiconductor substrate by a suitable implant, the first amorphous layer having a first depth, c) implanting a first dopant into the semiconductor substrate to provide the first amorphous layer with a first doping profile, d) applying a first solid phase epitaxial regrowth action to partially regrow the first amorphous layer and form a second amorphous layer having a second depth that is less than the first depth and activate the first dopant, e) implanting a second dopant into the semiconductor substrate to provide the second amorphous layer with a second doping profile with a higher doping concentration than the first doping profile, f) applying a second solid phase epitaxial regrowth action to regrow the second amorphous layer and activate the second dopant.

Abstract: A method of making a semiconductor device is disclosed. A semiconductor body, an STI region, a gate and a silicided source/drain region are provided. The STI area is etched, and a liner is formed at the upper surface.

Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

Abstract: A method of making a semiconductor device is disclosed. A semiconductor body, a gate electrode and source/drain regions are provided. A liner is provided that covers the gate electrode and the source/drain regions. Silicide regions are formed on the semiconductor device by etching a contact hole through the liner.

Abstract: A method of forming an isolation trench structure is disclosed, the method includes forming an isolation trench in a semiconductor body associated with an isolation region, and implanting a non-dopant atom into the isolation trench, thereby forming a region to modify the halo profile in the semiconductor body. Subsequently, the isolation trench is filled with a dielectric material.

Abstract: An ESD protection device includes a semiconductor body, a gate formed over a channel in the semiconductor body, the channel being doped with a first concentration of dopants of a first conductivity type. A first source/drain region is formed on the surface of the semiconductor body adjacent to a first edge of the gate, wherein the first source/drain region is doped with a dopant of a second conductivity type opposite the first conductivity type, and at least a portion of the first source/drain region is doped with a dopant of the first conductivity type. The concentration of the second conductivity type dopant exceeds the concentration of the first conductivity type dopant, and the concentration of the first conductivity type dopant in the first source/drain exceeds the first concentration.

Abstract: A method of making a semiconductor device is disclosed. A semiconductor body, an STI region, a gate and a silicided source/drain region are provided. The STI area is etched, and a liner is formed at the upper surface.

Abstract: To form a semiconductor device, an electrode layer is formed over a semiconductor body. The electrode layer includes an amorphous portion. A liner, e.g., a stress-inducing liner, is deposited over the electrode layer. The electrode layer is annealed to recrystallize the amorphous portion of the electrode layer. The liner can then be removed and an electronic component (e.g., a transistor) that includes a feature (e.g., a gate) formed from the electrode layer can be formed.

Abstract: A method of making a semiconductor device is disclosed. A first heavily doped region of a first conductivity type is implanted in a first portion of the semiconductor body and a first upper surface anneal is performed. After performing the first upper surface anneal, a second heavily doped region of a second conductivity type is implanted in a second portion of the semiconductor body. After implanting the second heavily doped region, a second upper surface anneal is performed.

Abstract: A semiconductor structure includes a base semiconductor substrate having a doped region located therein, and an epitaxial region located over the doped region. The semiconductor structure also includes a final isolation region located with the doped region and the epitaxial region. The final isolation region has a greater linewidth within the doped region than within the epitaxial region. A method for fabricating the semiconductor structure provides for forming the doped region prior to the epitaxial region. The doped region may be formed with reduced well implant energy and reduced lateral straggle. The final isolation region with the variable linewidth provides a greater effective isolation depth than an actual trench isolation depth.

Abstract: A method of making a semiconductor device is disclosed. An upper surface of a semiconductor body is amorphized and a liner is formed over the amorphized upper surface. The upper surface can then be annealed. A transistor is formed at the upper surface.

Abstract: A substrate having a buried well is provided. The substrate may be formed by implanting ions in a surface well of a first substrate and subsequently forming a semiconductor layer, such as an epitaxial layer, over the surface well. In this manner, the surface well becomes a buried well having a semiconductor layer that is substantially undoped formed thereon. In an embodiment, a transistor is formed on the substrate. Because the epitaxial layer is substantially undoped, the transistor may be formed such that the junction capacitance between the source/drain regions and the underlying region is reduced. If desired, the epitaxial layer, or a portion thereof, may be doped to decrease the resistance between the channel region and the well contact.

Abstract: An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming an isolation region between a first and a second region in a substrate, forming a recess in the substrate surface, and lining the recess with a uniform oxide. Embodiments further include doping a channel region under the bottom recess surface in the first and second regions and depositing a gate electrode material in the recess. Preferred embodiments include forming source/drain regions adjacent the channel region in the first and second regions, preferably after the step of depositing the gate electrode material. Another embodiment of the invention provides a semiconductor device comprising a recess in a surface of the first and second active regions and in the isolation region, and a dielectric layer having a uniform thickness lining the recess.

Abstract: A tiltable mounting as claimed in any of the preceding claims, wherein the lever has a conical shaped roller engaging the cam, the roller being mounted for rotation on the lever about an axis which passes through the pivotal axis of the lever and the conical surface of the roller having a projected apex which coincides with the pivotal axis of the roller to minimise sliding movement at the line of contact of the roller and cam as the roller moves over the cam surface.

Abstract: A slider used in a disk drive apparatus is described which has an air bearing surface and a trailing surface and a plurality of recessed steps at the trailing edge. These steps at the trailing edge greatly reduce stictional forces.