Patents by Inventor Richard Q. Williams

Richard Q. Williams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190288091
    Abstract: The present invention provides for a method of fabricating a semiconductor device, the method includes depositing a nitride layer on an ETSOI layer; forming a dummy gate over the nitride layer; forming nitride gate spacers from the nitride layer; growing a sacrificial layer on the ETSOI layer, the sacrificial layer composing a material that can be at least partially converted to a metal layer by a metal-bearing gas; forming refractory metal contacts using the sacrificial layer and a consumptive process; depositing an oxide protect layer on the refractory metal contacts; removing the dummy gate using a mask and etch process combined with chemical-mechanical polishing (CMP); etching the ETSOI layer to form a U-shaped channel; and depositing the final gate stack into the U-shaped channel.
    Type: Application
    Filed: March 15, 2018
    Publication date: September 19, 2019
    Inventors: Robert H. Dennard, Rajiv V. Joshi, Richard Q. Williams
  • Patent number: 10374046
    Abstract: A structure of a semiconductor device is described. In one aspect of the invention, a FinFET semiconductor device includes a FinFET transistor which includes a source region and a drain region disposed in a fin on a first surface of a substrate. A gate structure is disposed over a central portion of the fin. A wiring layer of conductive material is disposed over a second surface of the substrate which is opposite to the first surface of the substrate. A set of contact studs include a first contact stud which extends completely through the height of the fin in the source region and the substrate to the wiring layer. The set of contact studs also includes a second contact stud which extends completely through the height of the fin in the drain region and the substrate to the wiring layer. In other aspects of the invention, the device is a Nanosheet device or an inverter.
    Type: Grant
    Filed: January 2, 2017
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Carl J Radens, Richard Q Williams
  • Publication number: 20190189760
    Abstract: A structure of a semiconductor device is described. A semiconductor device includes a transistor which further includes a gate structure, a source region and a drain region disposed on a first surface of a substrate. A wiring layer of conductive material is disposed over a second surface of the substrate. The second surface of the substrate is located opposite to the first surface of the substrate. A set of contact studs including a first contact stud which extends completely through the source region and through the substrate to a first respective portion of the wiring layer. The set of contact studs also includes a second contact stud which extends completely through the drain region and through the substrate to a second respective portion of the wiring layer. A gate contact stud electrically couples the gate structure and extends completely through the substrate to a third respective portion of the wiring layer disposed over the second surface of the substrate.
    Type: Application
    Filed: February 26, 2019
    Publication date: June 20, 2019
    Inventors: Carl J Radens, Richard Q Williams
  • Patent number: 10269905
    Abstract: A structure of a semiconductor device is described. A semiconductor device includes a transistor which further includes a gate structure, a source region and a drain region disposed on a first surface of a substrate. A wiring layer of conductive material is disposed over a second surface of the substrate. The second surface of the substrate is located opposite to the first surface of the substrate. A set of contact studs including a first contact stud which extends completely through the source region and through the substrate to a first respective portion of the wiring layer. The set of contact studs also includes a second contact stud which extends completely through the drain region and through the substrate to a second respective portion of the wiring layer.
    Type: Grant
    Filed: January 2, 2017
    Date of Patent: April 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Carl J Radens, Richard Q Williams
  • Patent number: 9825172
    Abstract: The disclosure relates generally to a metal-oxide-semiconductor field effect transistor (MOSFET) structures and methods of forming the same. The MOSFET structure includes at least one semiconductor body on a substrate; a dielectric cap on a top surface of the at least one semiconductor body, wherein a width of the at least one semiconductor body is less than a width of the dielectric cap; a gate dielectric layer conformally coating the at least one semiconductor body; and at least one electrically conductive gate on the gate dielectric layer.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: November 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Edward J. Nowak, Richard Q. Williams
  • Publication number: 20170179244
    Abstract: A structure of a semiconductor device is described. In one aspect of the invention, a FinFET semiconductor device includes a FinFET transistor which includes a source region and a drain region disposed in a fin on a first surface of a substrate. A gate structure is disposed over a central portion of the fin. A wiring layer of conductive material is disposed over a second surface of the substrate which is opposite to the first surface of the substrate. A set of contact studs include a first contact stud which extends completely through the height of the fin in the source region and the substrate to the wiring layer. The set of contact studs also includes a second contact stud which extends completely through the height of the fin in the drain region and the substrate to the wiring layer. In other aspects of the invention, the device is a Nanosheet device or an inverter.
    Type: Application
    Filed: January 2, 2017
    Publication date: June 22, 2017
    Inventors: Carl J. Radens, Richard Q. Williams
  • Publication number: 20170179243
    Abstract: A structure of a semiconductor device is described. A semiconductor device includes a transistor which further includes a gate structure, a source region and a drain region disposed on a first surface of a substrate. A wiring layer of conductive material is disposed over a second surface of the substrate. The second surface of the substrate is located opposite to the first surface of the substrate. A set of contact studs including a first contact stud which extends completely through the source region and through the substrate to a first respective portion of the wiring layer. The set of contact studs also includes a second contact stud which extends completely through the drain region and through the substrate to a second respective portion of the wiring layer.
    Type: Application
    Filed: January 2, 2017
    Publication date: June 22, 2017
    Inventors: Carl J. Radens, Richard Q. Williams
  • Publication number: 20170161425
    Abstract: Methodologies for compact modeling of circuit layouts to accurately account for effects of layout-induced changes in semiconductor devices induced by various intentional and unintentional mechanisms present in semiconductor processes are disclosed. The layout-sensitive compact model accounts for the impact of large layout variation on circuits by implementing techniques for obtaining the correct layout-dependent response approximations and by incorporating layout extraction techniques to obtain correct geometric parameters that drive the LDE response. In particular, these techniques include utilizing shape sections for analyzing in detail various specific region shapes of the semiconductor device. The shape sections are defined by locating vertices of each region shape and rendering reference lines at each vertex.
    Type: Application
    Filed: December 3, 2015
    Publication date: June 8, 2017
    Inventors: Mitchell R. DeHond, Ulrich A. Finkler, Harold E. Reindel, Steven E. Washburn, Richard Q. Williams
  • Patent number: 9646124
    Abstract: In a system and method, a design layout defines a transistor, a local layout effect (LLE)-inducing feature and shapes, including a non-uniform shape, that illustrate separation between the channel region and LLE-inducing feature. Layout information for the non-uniform shape, including minimum and maximum distances between the channel region and LLE-inducing feature, is extracted. Based on this layout information, a first width of a first portion of the non-uniform shape, which is associated with the maximum distance, and a second width of a second portion of the non-uniform shape, which is associated with the minimum distance, are derived and used to calculate the non-uniform shape's contribution to the value of a model parameter adjuster. The value of the model parameter adjuster is then calculated based on a sum of contributions from all shapes and used to generate a compact model for modeling a performance attribute of the transistor within the IC.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: May 9, 2017
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Richard Q. Williams
  • Patent number: 9601570
    Abstract: A structure of a semiconductor device is described. A device structure including a gate structure, a source region and a drain region is disposed on a first surface of a substrate. Contact holes are etched through the source and drain regions and through a first portion of the substrate. The contact holes are filled with a conductive material to produce contact studs coupled to the source and drain regions. A second portion of the substrate is removed. A surface of the contact studs is exposed through a second surface of the substrate opposite to the gate structure for connection to a wiring layer disposed over the second surface of the substrate.
    Type: Grant
    Filed: July 31, 2016
    Date of Patent: March 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Carl J Radens, Richard Q Williams
  • Publication number: 20160378888
    Abstract: In a system and method, a design layout defines a transistor, a local layout effect (LLE)-inducing feature and shapes, including a non-uniform shape, that illustrate separation between the channel region and LLE-inducing feature. Layout information for the non-uniform shape, including minimum and maximum distances between the channel region and LLE-inducing feature, is extracted. Based on this layout information, a first width of a first portion of the non-uniform shape, which is associated with the maximum distance, and a second width of a second portion of the non-uniform shape, which is associated with the minimum distance, are derived and used to calculate the non-uniform shape's contribution to the value of a model parameter adjuster. The value of the model parameter adjuster is then calculated based on a sum of contributions from all shapes and used to generate a compact model for modeling a performance attribute of the transistor within the IC.
    Type: Application
    Filed: June 24, 2015
    Publication date: December 29, 2016
    Inventors: Dureseti Chidambarrao, Richard Q. Williams
  • Patent number: 9373678
    Abstract: Disclosed are non-planar capacitors with finely tuned capacitances and methods of forming them. The capacitors each incorporate one or more semiconductor bodies and one or more gate stacks traversing the one or more semiconductor bodies. At least one first semiconductor body is etched so that it is shorter in length than the others, which are incorporated into other non-planar devices and/or into the same non-planar capacitor. Additionally, at least one gate stack can be formed so that it traverses a first portion and, particularly, an end portion of the shortened semiconductor body and further so that it extends laterally some distance beyond that first portion. In such capacitors, the length of the first portion of the shorted semiconductor body, which corresponds to a capacitor conductor and which is traversed by the gate stack, which corresponds to a capacitor dielectric and another capacitor conductor, is predetermined to achieve a desired capacitance.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: June 21, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Edward J. Nowak, Richard Q. Williams
  • Publication number: 20150364534
    Abstract: Disclosed are non-planar capacitors with finely tuned capacitances and methods of forming them. The capacitors each incorporate one or more semiconductor bodies and one or more gate stacks traversing the one or more semiconductor bodies. At least one first semiconductor body is etched so that it is shorter in length than the others, which are incorporated into other non-planar devices and/or into the same non-planar capacitor. Additionally, at least one gate stack can be formed so that it traverses a first portion and, particularly, an end portion of the shortened semiconductor body and further so that it extends laterally some distance beyond that first portion. In such capacitors, the length of the first portion of the shorted semiconductor body, which corresponds to a capacitor conductor and which is traversed by the gate stack, which corresponds to a capacitor dielectric and another capacitor conductor, is predetermined to achieve a desired capacitance.
    Type: Application
    Filed: June 17, 2014
    Publication date: December 17, 2015
    Inventors: Edward J. Nowak, Richard Q. Williams
  • Patent number: 9178012
    Abstract: A method and structure is directed to eDRAM cells with high-conductance electrodes. The method includes forming upper layers on a semiconductor substrate and forming an opening in the upper layers. The method further includes forming a trench in the semiconductor substrate, aligned with the opening. The method further includes forming a metal plate on all exposed surface in the trench by applying a metallic aqueous solution with an electrical bias to a backside of the semiconductor substrate.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: November 3, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Veeraraghavan S. Basker, Richard Q. Williams
  • Patent number: 9058441
    Abstract: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (IOFF) in the statistical data using the DIBL data and the SS data and determining a model for a voltage to turn off the finFETs device (VOFF). The method also includes fitting the FinFET model to the VOFF.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Wilfried Ernest-August Haensch, Chung-Hsun Lin, Philip J. Oldiges, Hailing Wang, Richard Q. Williams
  • Patent number: 9059203
    Abstract: Disclosed is a semiconductor-on-insulator (SOI) structure (e.g., an SOI field effect transistor (FET)) and method of forming the SOI structure so as to have sub-insulator layer void(s) selectively placed so that capacitance coupling between a first section of a semiconductor layer and the substrate will be less than capacitance coupling between a second section of the semiconductor layer and the substrate. The first section may contain a first device and the second section may contain a second device. Alternatively, the first and second sections may comprise different regions of the same device. For example, in an SOI FET, sub-insulator layer voids can be selectively placed in the substrate below the source, drain and/or body contact diffusion regions, but not below the channel region so that capacitance coupling between the these various diffusion regions and the substrate will be less than capacitance coupling between the channel region and the substrate.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, Robert R. Robison, Richard Q. Williams
  • Publication number: 20140353755
    Abstract: The disclosure relates generally to a metal-oxide-semiconductor field effect transistor (MOSFET) structures and methods of forming the same. The MOSFET structure includes at least one semiconductor body on a substrate; a dielectric cap on a top surface of the at least one semiconductor body, wherein a width of the at least one semiconductor body is less than a width of the dielectric cap; a gate dielectric layer conformally coating the at least one semiconductor body; and at least one electrically conductive gate on the gate dielectric layer.
    Type: Application
    Filed: August 12, 2014
    Publication date: December 4, 2014
    Inventors: Edward J. Nowak, Richard Q. Williams
  • Publication number: 20140310676
    Abstract: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (IOFF) in the statistical data using the DIBL data and the SS data and determining a model for a voltage to turn off the finFETs device (VOFF). The method also includes fitting the FinFET model to the VOFF.
    Type: Application
    Filed: June 27, 2014
    Publication date: October 16, 2014
    Inventors: Wilfried Ernest-August Haensch, Chung-Hsun Lin, Philip J. Oldiges, Hailing Wang, Richard Q. Williams
  • Patent number: 8835261
    Abstract: The disclosure relates generally to a metal-oxide-semiconductor field effect transistor (MOSFET) structures and methods of forming the same. The MOSFET structure includes at least one semiconductor body on a substrate; a dielectric cap on a top surface of the at least one semiconductor body, wherein a width of the at least one semiconductor body is less than a width of the dielectric cap; a gate dielectric layer conformally coating the at least one semiconductor body; and at least one electrically conductive gate on the gate dielectric layer.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Edward J. Nowak, Richard Q. Williams
  • Patent number: 8806419
    Abstract: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (IOFF) in the statistical data using the DIBL data and the SS data and determining a model for a voltage to turn off the finFETs device (VOFF). The method also includes fitting the FinFET model to the VOFF.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Wilfried Ernest-August Haensch, Chung-Hsun Lin, Philip J. Oldiges, Hailing Wang, Richard Q. Williams