Patents by Inventor Richard Q. Williams
Richard Q. Williams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8835261Abstract: The disclosure relates generally to a metal-oxide-semiconductor field effect transistor (MOSFET) structures and methods of forming the same. The MOSFET structure includes at least one semiconductor body on a substrate; a dielectric cap on a top surface of the at least one semiconductor body, wherein a width of the at least one semiconductor body is less than a width of the dielectric cap; a gate dielectric layer conformally coating the at least one semiconductor body; and at least one electrically conductive gate on the gate dielectric layer.Type: GrantFiled: March 14, 2011Date of Patent: September 16, 2014Assignee: International Business Machines CorporationInventors: Edward J. Nowak, Richard Q. Williams
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Patent number: 8806419Abstract: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (IOFF) in the statistical data using the DIBL data and the SS data and determining a model for a voltage to turn off the finFETs device (VOFF). The method also includes fitting the FinFET model to the VOFF.Type: GrantFiled: August 20, 2013Date of Patent: August 12, 2014Assignee: International Business Machines CorporationInventors: Wilfried Ernest-August Haensch, Chung-Hsun Lin, Philip J. Oldiges, Hailing Wang, Richard Q. Williams
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Patent number: 8799848Abstract: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (IOFF) in the statistical data using the DIBL data and the SS data and determining a model for a voltage to turn off the finFETs device (VOFF). The method also includes fitting the FinFET model to the VOFF.Type: GrantFiled: January 15, 2013Date of Patent: August 5, 2014Assignee: International Business Machines CorporationInventors: Wilfried Ernest-August Haensch, Chung-Hsun Lin, Philip J. Oldiges, Hailing Wang, Richard Q. Williams
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Publication number: 20140201699Abstract: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (IOFF) in the statistical data using the DIBL data and the SS data and determining a model for a voltage to turn off the finFETs device (VOFF). The method also includes fitting the FinFET model to the VOFF.Type: ApplicationFiled: January 15, 2013Publication date: July 17, 2014Applicant: International Business Machines CorporationInventors: Wilfried Ernest-August HAENSCH, Chung-Hsun Lin, Philip J. Oldiges, Hailing Wang, Richard Q. Williams
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Publication number: 20140201700Abstract: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (IOFF) in the statistical data using the DIBL data and the SS data and determining a model for a voltage to turn off the finFETs device (VOFF). The method also includes fitting the FinFET model to the VOFF.Type: ApplicationFiled: August 20, 2013Publication date: July 17, 2014Applicant: International Business Machines CorporationInventors: Wilfried Ernest-August HAENSCH, Chung-Hsun Lin, Philip J. Oldiges, Hailing Wang, Richard Q. Williams
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Publication number: 20140151850Abstract: A method and structure is directed to eDRAM cells with high-conductance electrodes. The method includes forming upper layers on a semiconductor substrate and forming an opening in the upper layers. The method further includes forming a trench in the semiconductor substrate, aligned with the opening. The method further includes forming a metal plate on all exposed surface in the trench by applying a metallic aqueous solution with an electrical bias to a backside of the semiconductor substrate.Type: ApplicationFiled: February 7, 2014Publication date: June 5, 2014Applicant: International Business Machines CorporationInventors: Veeraraghavan S. BASKER, Richard Q. WILLIAMS
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Patent number: 8745571Abstract: The disclosure relates to the analysis of compensated layout shapes. A method in accordance with an embodiment includes: analyzing a semiconductor layout using a bucket structure, the layout including a semiconductor device; and applying a pattern template to a content of the bucket structure to identify a shape adjacent to the semiconductor device; wherein the pattern template is derived from layout groundrules.Type: GrantFiled: February 14, 2011Date of Patent: June 3, 2014Assignee: International Business Machines CorporationInventors: Hongmei Li, Richard Q. Williams
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Patent number: 8703572Abstract: A method and structure is directed to eDRAM cells with high-conductance electrodes. The method includes forming upper layers on a semiconductor substrate and forming an opening in the upper layers. The method further includes forming a trench in the semiconductor substrate, aligned with the opening. The method further includes forming a metal plate on all exposed surface in the trench by applying a metallic aqueous solution with an electrical bias to a backside of the semiconductor substrate.Type: GrantFiled: October 10, 2011Date of Patent: April 22, 2014Assignee: International Business Machines CorporationInventors: Veeraraghavan S. Basker, Richard Q. Williams
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Publication number: 20140021548Abstract: Disclosed is a semiconductor-on-insulator (SOI) structure (e.g., an SOI field effect transistor (FET)) and method of forming the SOI structure so as to have sub-insulator layer void(s) selectively placed so that capacitance coupling between a first section of a semiconductor layer and the substrate will be less than capacitance coupling between a second section of the semiconductor layer and the substrate. The first section may contain a first device and the second section may contain a second device. Alternatively, the first and second sections may comprise different regions of the same device. For example, in an SOI FET, sub-insulator layer voids can be selectively placed in the substrate below the source, drain and/or body contact diffusion regions, but not below the channel region so that capacitance coupling between the these various diffusion regions and the substrate will be less than capacitance coupling between the channel region and the substrate.Type: ApplicationFiled: September 25, 2013Publication date: January 23, 2014Applicant: International Business Machines CorporationInventors: Toshiharu Furukawa, Robert R. Robison, Richard Q. Williams
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Patent number: 8610211Abstract: Disclosed is a semiconductor-on-insulator (SOI) structure having sub-insulator layer void(s) selectively placed in a substrate so that capacitance coupling between a first section of a semiconductor layer and the substrate will be less than capacitance coupling between a second section of the semiconductor layer and the substrate. The first section may contain a first device on an insulator layer and the second section may contain a second device on the insulator layer. Alternatively, the first and second sections may comprise different regions of the same device on an insulator layer. For example, in an SOI field effect transistor (FET), sub-insulator layer voids can be selectively placed in the substrate below the source, drain and/or body contact diffusion regions, but not below the channel region so that capacitance coupling between the these various diffusion regions and the substrate will be less than capacitance coupling between the channel region and the substrate.Type: GrantFiled: July 23, 2010Date of Patent: December 17, 2013Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, Robert R. Robison, Richard Q. Williams
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Patent number: 8453100Abstract: A method (and computer program) identify shapes and locations of transistor elements within a geometric circuit layout. The transistor elements include an active area, at least one gate conductor and other transistor elements. Also, the gate conductor has sides running in a first direction, and has a width dimension running in a second direction perpendicular to the first direction. The method defines regions within the geometric circuit layout. To do so, the method defines a first region having a perimeter positioned along the sides of the gate conductor where the gate conductor intersects the active area and then expands the perimeter of the first region in the second direction to edges of the active area to define a perimeter of a second region. The first region and the second share perimeters in the first direction. The method then expands the perimeter of the second region in the first direction to define a perimeter of a third region.Type: GrantFiled: September 1, 2010Date of Patent: May 28, 2013Assignee: International Business Machines CorporationInventors: Dureseti Chidambarrao, Richard Q. Williams
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Publication number: 20130087841Abstract: A method and structure is directed to eDRAM cells with high-conductance electrodes. The method includes forming upper layers on a semiconductor substrate and forming an opening in the upper layers. The method further includes forming a trench in the semiconductor substrate, aligned with the opening.Type: ApplicationFiled: October 10, 2011Publication date: April 11, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Veeraraghavan S. BASKER, Richard Q. WILLIAMS
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Patent number: 8417503Abstract: A method and structure for a computer model of a device has a performance parameter. The performance parameter includes a first bounded range and a second bounded range. The first bounded range has performance parameter variations within a single manufacturing process, and the second bounded range has performance parameter variations of different device designs.Type: GrantFiled: December 17, 2001Date of Patent: April 9, 2013Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Josef S. Watts, Richard Q. Williams
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Patent number: 8392867Abstract: A system and method for developing condensed netlists for sub-circuits within an integrated circuit and for modeling the performance of the integrated circuit based on the condensed netlists rather than full netlists. An IC layout is segmented into a plurality of sub-circuits, each comprising a group of one or more of a given type of active devices connected to (i.e., sharing) the same electrical sub-circuit terminals through a similar resistive network (i.e. such that they are subjected to approximately the same overall combined parasitic resistances). Full netlists corresponding to the sub-circuits are extracted from the layout and condensed. Each condensed netlist accounts for performance variations (e.g., as a function of variations in operating power supply voltages, operating temperatures and, optionally, self-heating and/or stress) exhibited by the active devices and resistive network in a sub-circuit.Type: GrantFiled: January 13, 2011Date of Patent: March 5, 2013Assignee: International Business Machines CorporationInventors: Yanqing Deng, Paul A. Hyde, James M. Johnson, Todd G. McKenzie, Scott K. Springer, Richard Q. Williams
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Publication number: 20120235233Abstract: The disclosure relates generally to a metal-oxide-semiconductor field effect transistor (MOSFET) structures and methods of forming the same. The MOSFET structure includes at least one semiconductor body on a substrate; a dielectric cap on a top surface of the at least one semiconductor body, wherein a width of the at least one semiconductor body is less than a width of the dielectric cap; a gate dielectric layer conformally coating the at least one semiconductor body; and at least one electrically conductive gate on the gate dielectric layer.Type: ApplicationFiled: March 14, 2011Publication date: September 20, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edward J. Nowak, Richard Q. Williams
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Publication number: 20120210283Abstract: The disclosure relates to the analysis of compensated layout shapes. A method in accordance with an embodiment includes: analyzing a semiconductor layout using a bucket structure, the layout including a semiconductor device; and applying a pattern template to a content of the bucket structure to identify a shape adjacent to the semiconductor device; wherein the pattern template is derived from layout groundrules.Type: ApplicationFiled: February 14, 2011Publication date: August 16, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hongmei Li, Richard Q. Williams
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Publication number: 20120185812Abstract: A system and method for developing condensed netlists for sub-circuits within an integrated circuit and for modeling the performance of the integrated circuit based on the condensed netlists rather than full netlists. An IC layout is segmented into a plurality of sub-circuits, each comprising a group of one or more of a given type of active devices connected to (i.e., sharing) the same electrical sub-circuit terminals through a similar resistive network (i.e. such that they are subjected to approximately the same overall combined parasitic resistances). Full netlists corresponding to the sub-circuits are extracted from the layout and condensed. Each condensed netlist accounts for performance variations (e.g., as a function of variations in operating power supply voltages, operating temperatures and, optionally, self-heating and/or stress) exhibited by the active devices and resistive network in a sub-circuit.Type: ApplicationFiled: January 13, 2011Publication date: July 19, 2012Applicant: International Business Machines CorporationInventors: Yanqing Deng, Paul A. Hyde, James M. Johnson, Todd G. McKenzie, Scott K. Springer, Richard Q. Williams
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Patent number: 8211741Abstract: Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.Type: GrantFiled: June 28, 2011Date of Patent: July 3, 2012Assignee: International Business Machines CorporationInventors: Joerg Appenzeller, AJ Kleinosowski, Edward J. Nowak, Richard Q. Williams
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Publication number: 20120054711Abstract: A method (and computer program) identify shapes and locations of transistor elements within a geometric circuit layout. The transistor elements include an active area, at least one gate conductor and other transistor elements. Also, the gate conductor has sides running in a first direction, and has a width dimension running in a second direction perpendicular to the first direction. The method defines regions within the geometric circuit layout. To do so, the method defines a first region having a perimeter positioned along the sides of the gate conductor where the gate conductor intersects the active area and then expands the perimeter of the first region in the second direction to edges of the active area to define a perimeter of a second region. The first region and the second share perimeters in the first direction. The method then expands the perimeter of the second region in the first direction to define a perimeter of a third region.Type: ApplicationFiled: September 1, 2010Publication date: March 1, 2012Applicant: International Business Machines CorporationInventors: Dureseti Chidambarrao, Richard Q. Williams
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Patent number: 8119474Abstract: A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first plate and the second plate.Type: GrantFiled: January 15, 2010Date of Patent: February 21, 2012Assignee: International Business Machines CorporationInventors: Andres Bryant, Edward J. Nowak, Richard Q. Williams