Abstract: A method for fabricating a connector structure for interconnecting integrated circuit chips. The method includes the steps of patterning, masking and etching a substrate to form protrusions on the top and/or bottom surfaces of the substrate. Then the protrusions are preferentially etched to form truncated protrusions. An integrated circuit chip having pads on its surface is then joined to the top and/or bottom sides of the substrate. The protrusions and pads are coated with an electrically conductive metal. The substrate and the integrated circuit chips are joined and aligned together such that the truncated protrusions mate with the pads. Metal-coated vias are formed through the substrate to electrically connect the integrated circuit chips on the surfaces of the substrate.

Abstract: An ESD protection method and apparatus are provided for an IC chip having an I/O pad and I/O circuitry coupled to the I/O pad. A low threshold voltage FET is coupled to the I/O pad in parallel with the I/O circuitry for protecting the IC chip from an ESD event on the I/O pad. The FET also is coupled to a first voltage terminal of the I/O circuitry for providing a shunting path for the ESD event, thereby effectuating the protecting of the IC chip from the ESD event on the I/O pad. A first control circuit is coupled to a gate of the FET for maintaining the gate at a voltage level below a threshold voltage of the FET, thereby maintaining the FET in an off state during normal operation of the IC chip. Preferably a second control circuit is coupled between the FET and the first voltage terminal and operates in conjunction with the first control circuit for maintaining the FET in an off state during normal operation of the IC chip.

Abstract: An apparatus and method for detecting a defective array of NVRAM cells. A counter is provided which times an erase time interval for the NVRAM cells during a regular erase function. The computed erase interval is compared with a maximum erase interval to determine at least a first characteristic which indicates the block of NVRAMs is at the end of its useful life. A second characteristic is determined by computing the slope in the erase time function versus the number of simulated erase functions. When the slope of the erase function exceeds a maximum slope, the NVRAM array is determined to be at the end of its useful life.

Abstract: A method for fabricating an interconnected multiple circuit chip structure by etching a first substrate to form protrusions on its surface. Then the protrusions are preferentially etched to produce a selected shape such as a tetragonal protrusion and an integrated circuit is then fabricated on the substrate. A second substrate is preferentially etched to form recesses having a selected shape that is the complement of the selected shape of the protrusions of the first substrate and then an integrated circuit is fabricated on the second substrate. The protrusions and recesses are coated with an electrically conductive metal such as aluminum. The first and second substrates are joined and aligned together such that the protrusions mate with the recesses and the structure is annealed such that the metal coatings thereon come into contact to electrically connect the integrated circuits on the substrates. The method can also be used to electrically connect multiple chips mounted back to front.

Abstract: A nonvolatile memory cell comprises a conductive cantilever beam having a free end in a first charge state, a first FET having a conductive gate in a second charge state and a pull-in electrode adapted to bring the cantilever beam into electrical contact with the gate to effect a charge state change in the gate. A pull-in electrode input is connected to the electrode, a cantilever input is connected to the cantilever, a column select input is connected to the first FET and a row select input is connected to the first FET. The nonvolatile memory cell is selected by signals applied to the row select input and the column select input. The cell also includes a second FET connected between the cantilever beam and the cantilever input for controlling the passage of signals from the cantilever input to the cantilever beam and a third FET connected between the pull-in electrode and the pull-in electrode input for controlling the passage of signals from the pull-in electrode input to the electrode.

Abstract: Breakdown and latch-up of field effect transistors integrated with non-volatile semiconductor memory cells requiring voltages higher than logic level voltages for write and erase operations is avoided while limiting process complexity and constraints and increasing potential integration density by using thin film transistors for high voltage switching and isolating the thin film transistors from the substrate by forming the thin film transistors on isolation structures extending between or over elements formed at a surface of a substrate or semiconductor layer. Geometry and doping levels of the thin film transistors is thus made independent of geometry and doping levels of the non-volatile semiconductor memory cells and other field effect transistors operating at lower logic-level voltages.