Abstract: The present invention relates generally to integrated circuit (IC) chip packaging, and more particularly, to a structure and method of forming a glass interposer having thermally conductive vias in addition to electrically conductive vias. The thermally conductive vias help dissipate heat from one or more IC chips, through the glass interposer, into an organic carrying, and then, into an underlying substrate where it can be dissipated.

Abstract: A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may consist of a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.

Abstract: A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may include a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.

Abstract: A chip fabricated from a semiconductor material is disclosed, which may include active devices located below a first depth from the chip back side, and a structure to remove heat from the active devices to the chip back side. The structure may include thermally conductive partial vias (TCPVs), which may include a recess with a depth, from the chip back side towards the active devices less than the first depth. Each TCPV may include a barrier layer deposited within the recess and deposited upon the back side of the chip. Each TCPV may also include a thermally conductive layer deposited upon the barrier layer. The structure may also include through-silicon vias (TSVs) electrically connected to active devices, extending from the back side to an active device side of the chip to conductively remove heat from the active devices to the back side of the chip.

Abstract: Embodiments of the invention relate to incorporating one or more antennas or inductor coils into a semi-conductor package. A heat spreader or metal sheet is embedded in the package and stamped or otherwise patterned into a spiral or serpentine form. The pattern enables the spreader to function as an inductor or antenna when connected to a semiconductor chip in communication with a printed circuit board.

Abstract: A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may consist of a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.

Abstract: A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads.

Abstract: Various particular embodiments include a method of forming an integrated circuit (IC) device including: forming at least one thermoelectric cooling device over an upper surface of a handle wafer based upon a known location of an elevated temperature region in the IC device; forming a first oxide layer over the handle wafer covering the thermoelectric cooling device; forming a second oxide layer over a donor silicon wafer to form a donor wafer; bonding the donor wafer to the handle wafer at the first oxide layer and the second oxide layer, such that the second oxide layer contacts the first oxide layer on the handle wafer; and forming at least one semiconductor device over the donor silicon wafer side of the donor wafer, wherein the at least one thermoelectric cooling device is located proximate the at least one semiconductor device.

Abstract: Mechanisms are provided for sacrificial carrier dicing of semiconductor wafers. A bottom layer of a semiconductor wafer is bonded to a top layer of a sacrificial carrier. The semiconductor wafer is diced into a set of chips, such that the dicing cuts through the semiconductor wafer and into the sacrificial carrier and such that the sacrificial carrier dresses a diamond blade of a saw so as to expose one or more new, sharp layers of diamonds on the diamond blade.

Abstract: Mechanisms are provided for sacrificial carrier dicing of semiconductor wafers. A bottom layer of a semiconductor wafer is bonded to a top layer of a sacrificial carrier. The semiconductor wafer is diced into a set of chips, such that the dicing cuts through the semiconductor wafer and into the sacrificial carrier and such that the sacrificial carrier dresses a diamond blade of a saw so as to expose one or more new, sharp layers of diamonds on the diamond blade.

Abstract: An electronic device includes a circuit board and a semiconductor device package. The semiconductor device package includes a laminate layer. The semiconductor device package includes a semiconductor die having an active side, an inactive side opposite the active side, and through-silicon vias (TSVs) conductively connecting the active side to the inactive side and conductively connecting the semiconductor die to one of the laminate layer and the circuit board. The semiconductor device package includes a laminate layer having a side attached to the active side or the inactive side semiconductor die. The semiconductor device package includes solder balls at the side of the laminate layer attached to the semiconductor die, around the semiconductor die, and attached to the circuit board.

Abstract: A first package includes a laminate layer, an overmold layer above and in direct contact with the laminate layer, and a logic circuit-through-silicon via (TSV) layer including a first logic die and TSVs. The logic circuit-TSV layer is within the overmold layer, and the TSVs are electrically exposed at a top surface of the overmold layer. The first package may be fabricated and tested by a first party prior to being provided to a second party. A second package includes a second logic die. The second party may attach the second package to the first package at the electrically exposed TSVs of the first package to realize a complete and functional semiconductor device.

Abstract: An electronic device includes a circuit board and a semiconductor device package. The semiconductor device package includes a laminate layer. The semiconductor device package includes a semiconductor die having an active side, an inactive side opposite the active side, and through-silicon vias (TSVs) conductively connecting the active side to the inactive side and conductively connecting the semiconductor die to one of the laminate layer and the circuit board. The semiconductor device package includes a laminate layer having a side attached to the active side or the inactive side semiconductor die. The semiconductor device package includes solder balls at the side of the laminate layer attached to the semiconductor die, around the semiconductor die, and attached to the circuit board.

Abstract: Various embodiments include wafer level chip scale package (WLCSP) structures and methods of tuning such structures. In some embodiments, the WLCSP structure includes: a printed circuit board (PCB) trace connection including at least one PCB ground connection connected with a PCB ground plane; a set of ground solder balls each contacting the printed circuit board trace connection; a set of chip pads contacting each of the ground solder balls in the set of ground solder balls; a chip ground plane connecting the set of chip pads; and a signal interconnect interposed between two of the set of ground solder balls, the signal interconnect including: a signal trace connection electrically isolated from the PCB ground plane; a signal ball contacting the signal PCB trace connection; a chip pad contacting the signal ball, and a signal trace connection on a chip contacting the chip pad.

Abstract: Various embodiments include managing metal densities in kerf sections of an integrated circuit (IC) wafer. In some embodiments, a method includes: forming an integrated circuit (IC) wafer including a wafer kerf region, the wafer kerf region having a metal density of less than approximately 0.5 percent relative to a total density of the wafer kerf region.

Abstract: A chip fabricated from a semiconductor material is disclosed. The chip may include active devices located below a first depth from a chip back side and a structure configured to remove heat from the chip. The structure may include microvias electrically insulated from the active devices and having a second depth, less than the first depth, from the back side towards the active devices. Each microvia may also have a fill material having a thermal conductivity greater than a semiconductor thermal conductivity. The structure may also include thermally conductive material regions on the back side of the chip in contact with sets of microvias. The structure may also include through-silicon vias electrically connected to the active devices, and extending from the back side to an active device side of the chip and configured to remove heat from the active devices to the back side of the chip.

Abstract: Various embodiments include wafer level chip scale package (WLCSP) structures and methods of tuning such structures. In some embodiments, the WLCSP structure includes: a printed circuit board (PCB) trace connection including at least one PCB ground connection connected with a PCB ground plane; a set of ground solder balls each contacting the printed circuit board trace connection; a set of chip pads contacting each of the ground solder balls in the set of ground solder balls; a chip ground plane connecting the set of chip pads; and a signal interconnect interposed between two of the set of ground solder balls, the signal interconnect including: a signal trace connection electrically isolated from the PCB ground plane; a signal ball contacting the signal PCB trace connection; a chip pad contacting the signal ball, and a signal trace connection on a chip contacting the chip pad.

Abstract: Various embodiments include managing metal densities in kerf sections of an integrated circuit (IC) wafer. In some embodiments, a method includes: forming an integrated circuit (IC) wafer including a wafer kerf region, the wafer kerf region having a metal density of less than approximately 0.5 percent relative to a total density of the wafer kerf region.

Abstract: Embodiments of the invention relate to incorporating one or more antennas or inductor coils into a semi-conductor package. A heat spreader or metal sheet is embedded in the package and stamped or otherwise patterned into a spiral or serpentine form. The pattern enables the spreader to function as an inductor or antenna when connected to a semiconductor chip in communication with a printed circuit board.

Abstract: A heat conductive layer is deposited on a first surface of a wafer of semiconductor chips. The heat conductive layer is etched to form vias that expose through-electrodes on the first surface of each semiconductor chip. Conductive bumps are deposited on the through-electrodes on a second surface of each semiconductor chip. The semiconductor chips are stacked, wherein the conductive bumps of a second one of the semiconductor chips electrically contact the through-electrodes of a first one of the semiconductor chips through the vias of the first semiconductor chip and the conductive bumps of a third one of the semiconductor chips electrically contact the through-electrodes of the second semiconductor chip through the vias of the second semiconductor chip.