Patents by Inventor Riki SUZUKI

Riki SUZUKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210293681
    Abstract: An information processing apparatus (2000) acquires time-series data (14) output by a sensor (10) and computes a contribution value ?i representing contribution with respect to the time-series data (14) for each of a plurality of feature constants ?i. Thereafter, the information processing apparatus (2000) outputs a set ? of the contribution values ?i as a feature value of a target gas. As the feature constant ?, a velocity constant ? or a time constant ? that is a reciprocal of the velocity constant can be adopted.
    Type: Application
    Filed: July 31, 2018
    Publication date: September 23, 2021
    Applicant: NEC Corporation
    Inventors: Ryota SUZUKI, Riki ETO
  • Publication number: 20210295921
    Abstract: A memory system includes a non-volatile memory having a plurality of memory cells and a controller. The controller is configured to switch a mode for controlling an access operation to the non-volatile memory from a first mode to a second mode, in response to receiving from a host, a first command for instructing the controller to switch the mode from the first mode to the second mode. The access operation controlled according to the second mode improves data retention relative to the access operation controlled according to the first mode.
    Type: Application
    Filed: February 25, 2021
    Publication date: September 23, 2021
    Inventors: Riki SUZUKI, Yoshihisa KOJIMA
  • Patent number: 11099783
    Abstract: A memory system includes a non-volatile memory chip that includes a memory cell array, and a memory controller. The memory controller is configured to perform a read operation on the non-volatile memory chip by instructing the non-volatile memory chip to perform a sensing operation to read data stored in the memory cell array, estimating a time when the read data becomes ready to be transferred from the non-volatile memory chip to the memory controller, and instructing the non-volatile memory chip, after the estimated time, to perform a transfer operation to transfer the read data to the memory controller.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: August 24, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Marie Sia, Yoshihisa Kojima, Suguru Nishikawa, Riki Suzuki
  • Patent number: 11086718
    Abstract: A memory system includes a nonvolatile memory, a buffer, and a controller. The buffer can temporarily store a plurality of data bits to be written to the nonvolatile memory. The controller can write the plurality of data bits, read from the buffer, to the nonvolatile memory; write a plurality of intermediate parity bits to the buffer, but not to the nonvolatile memory, wherein each of the plurality of intermediate parity bits is associated with an error correction process on each of the plurality of data bits; and write, to the nonvolatile memory, an accumulated parity bit that is an integration of the plurality of intermediate parity bits.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: August 10, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Riki Suzuki, Toshikatsu Hida, Yoshihisa Kojima, Takehiko Amaki, Suguru Nishikawa
  • Patent number: 11069413
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller that controls operation of the nonvolatile memory. The nonvolatile memory is configured to receive, from the memory controller, a first command for execution of at least one of an erase operation and a program operation; in response to receiving a second command from the memory controller during execution of a first operation requested by the first command, execute a second operation for suspending the first operation before the first operation reaches a given section; and in response to receiving a third command from the memory controller during the execution of the first operation, suspend the first operation after the given section.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: July 20, 2021
    Assignee: Kioxia Corporation
    Inventors: Suguru Nishikawa, Riki Suzuki, Yoshihisa Kojima
  • Patent number: 11042310
    Abstract: A memory system includes a nonvolatile semiconductor memory including a first memory region for storing start-up information and a second memory region for storing a copy of the start-up information, a volatile semiconductor memory, and a controller. The controller is configured to determine whether or not an address of the second memory region is stored in the volatile semiconductor memory, issue a first start-up read command, which designates no read address, to the nonvolatile semiconductor memory to read the start-up information from the first memory region if the address of the second memory region is not stored in the volatile semiconductor memory, and issue a second start-up read command, which designates the address of the second memory region as a read address, to read the start-up information from the second memory region if the address of the second memory region is stored in the volatile semiconductor memory.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: June 22, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Riki Suzuki, Toshikatsu Hida, Takehiko Amaki, Shunichi Igahara
  • Publication number: 20210183877
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.
    Type: Application
    Filed: February 23, 2021
    Publication date: June 17, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Takehiko AMAKI, Yoshihisa KOJIMA, Toshikatsu HIDA, Marie Grace Izabelle Angeles SIA, Riki SUZUKI, Shohei ASAMI
  • Publication number: 20210175907
    Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.
    Type: Application
    Filed: February 18, 2021
    Publication date: June 10, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Riki SUZUKI, Toshikatsu HIDA, Osamu TORII, Hiroshi YAO, Kiyotaka IWASAKI
  • Patent number: 11004523
    Abstract: According to one embodiment, a nonvolatile memory includes: a memory cell array including memory cells; and a controller configured to execute a first refresh process on receiving a first command. The first refresh process includes reprogramming at least one second memory cell among first memory cells to which data has been programmed in a first group. In executing the first refresh process, the controller is configured to: select the second memory cell by verifying with a first voltage using a first amount in a case where the second memory cell has been programmed using the first voltage; and select the second memory cell by verifying with a second voltage using a second amount in a case where the second memory cell has been programmed using the second voltage.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: May 11, 2021
    Assignee: Toshiba Memory Coiporation
    Inventors: Riki Suzuki, Masanobu Shirakawa, Yoshihisa Kojima, Marie Takada, Tsukasa Tokutomi
  • Patent number: 10965324
    Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: March 30, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Riki Suzuki, Toshikatsu Hida, Osamu Torii, Hiroshi Yao, Kiyotaka Iwasaki
  • Patent number: 10964712
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: March 30, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Takehiko Amaki, Yoshihisa Kojima, Toshikatsu Hida, Marie Grace Izabelle Angeles Sia, Riki Suzuki, Shohei Asami
  • Publication number: 20210081276
    Abstract: A memory system includes a nonvolatile memory, a buffer, and a controller. The buffer can temporarily store a plurality of data bits to be written to the nonvolatile memory. The controller can write the plurality of data bits, read from the buffer, to the nonvolatile memory; write a plurality of intermediate parity bits to the buffer, but not to the nonvolatile memory, wherein each of the plurality of intermediate parity bits is associated with an error correction process on each of the plurality of data bits; and write, to the nonvolatile memory, an accumulated parity bit that is an integration of the plurality of intermediate parity bits.
    Type: Application
    Filed: March 2, 2020
    Publication date: March 18, 2021
    Applicant: KIOXIA CORPORATION
    Inventors: Riki SUZUKI, Toshikatsu HIDA, Yoshihisa KOJIMA, Takehiko AMAKI, Suguru NISHIKAWA
  • Patent number: 10895990
    Abstract: According to one embodiment, a memory system includes a first memory as a nonvolatile memory storing first data, second data as a translation table for accessing the first data, third data, fourth data as a translation table for accessing the third data, and including two memory cell arrays which are accessible in parallel, a second memory in which the second and fourth data is storable, and which stores a management table for managing information about whether the second and fourth data is stored in the second memory, a controller checking whether the second and fourth data is stored in the second memory based on the management table, a third memory storing an order of executing commands to be issued to the first memory, and a scheduler scheduling the order based on a result of the checking, two of a first command for reading the first data, a second command for reading the second data, a third command for reading the third data and a fourth command for reading the fourth data being executed in parallel in t
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: January 19, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Sayano Aga, Toshikatsu Hida, Riki Suzuki
  • Publication number: 20210005264
    Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Suguru NISHIKAWA, Yoshihisa KOJIMA, Riki SUZUKI, Masanobu SHIRAKAWA, Toshikatsu HIDA
  • Publication number: 20210004169
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.
    Type: Application
    Filed: September 22, 2020
    Publication date: January 7, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Shunichi Igahara, Toshikatsu Hida, Riki Suzuki, Takehiko Amaki, Suguru Nishikawa, Yoshihisa Kojima
  • Publication number: 20200402596
    Abstract: According to one embodiment, a nonvolatile memory includes: a memory cell array including memory cells; and a controller configured to execute a first refresh process on receiving a first command. The first refresh process includes reprogramming at least one second memory cell among first memory cells to which data has been programmed in a first group. In executing the first refresh process, the controller is configured to: select the second memory cell by verifying with a first voltage using a first amount in a case where the second memory cell has been programmed using the first voltage; and select the second memory cell by verifying with a second voltage using a second amount in a case where the second memory cell has been programmed using the second voltage.
    Type: Application
    Filed: August 31, 2020
    Publication date: December 24, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Riki Suzuki, Masanobu Shirakawa, Yoshihisa Kojima, Marie Takada, Tsukasa Tokutomi
  • Patent number: 10831395
    Abstract: According to one embodiment, a memory system includes a memory and a controller electrically connected to the memory. The memory includes blocks. Each of the blocks includes one or more sub-blocks. Each of the one or more sub-blocks includes nonvolatile memory cells. The controller is configured to obtain read frequency of at least one of the sub-blocks, and move data stored in the at least one of the sub-blocks so that data having substantially the same read frequency are written into one block.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: November 10, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Riki Suzuki, Yoshihisa Kojima, Toshikatsu Hida
  • Patent number: 10824353
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: November 3, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Shunichi Igahara, Toshikatsu Hida, Riki Suzuki, Takehiko Amaki, Suguru Nishikawa, Yoshihisa Kojima
  • Patent number: 10818358
    Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: October 27, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Suguru Nishikawa, Yoshihisa Kojima, Riki Suzuki, Masanobu Shirakawa, Toshikatsu Hida
  • Publication number: 20200326862
    Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The memory includes a memory cell array. The controller is configured to control a transfer phase in which a command, an address, and first data are transferred to the memory, and a program phase in which the first data is programmed into the memory cell array by the memory after the transfer phase. The controller is configured to suspend the transfer phase after initiating the transfer phase before completion of the transfer phase, then read second data from the memory, and resume the transfer phase after reading of the second data is completed.
    Type: Application
    Filed: June 26, 2020
    Publication date: October 15, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Shizuka ENDO, Riki SUZUKI, Yoshihisa KOJIMA