Abstract: According to one embodiment, a nonvolatile memory includes: a memory cell array including memory cells; and a controller configured to execute a first refresh process on receiving a first command. The first refresh process includes reprogramming at least one second memory cell among first memory cells to which data has been programmed in a first group. In executing the first refresh process, the controller is configured to: select the second memory cell by verifying with a first voltage using a first amount in a case where the second memory cell has been programmed using the first voltage; and select the second memory cell by verifying with a second voltage using a second amount in a case where the second memory cell has been programmed using the second voltage.

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.

Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.

Abstract: A memory system includes a nonvolatile memory, a buffer, and a controller. The buffer can temporarily store a plurality of data bits to be written to the nonvolatile memory. The controller can write the plurality of data bits, read from the buffer, to the nonvolatile memory; write a plurality of intermediate parity bits to the buffer, but not to the nonvolatile memory, wherein each of the plurality of intermediate parity bits is associated with an error correction process on each of the plurality of data bits; and write, to the nonvolatile memory, an accumulated parity bit that is an integration of the plurality of intermediate parity bits.

Abstract: According to one embodiment, a memory system includes a first memory as a nonvolatile memory storing first data, second data as a translation table for accessing the first data, third data, fourth data as a translation table for accessing the third data, and including two memory cell arrays which are accessible in parallel, a second memory in which the second and fourth data is storable, and which stores a management table for managing information about whether the second and fourth data is stored in the second memory, a controller checking whether the second and fourth data is stored in the second memory based on the management table, a third memory storing an order of executing commands to be issued to the first memory, and a scheduler scheduling the order based on a result of the checking, two of a first command for reading the first data, a second command for reading the second data, a third command for reading the third data and a fourth command for reading the fourth data being executed in parallel in t

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.

Abstract: According to one embodiment, a nonvolatile memory includes: a memory cell array including memory cells; and a controller configured to execute a first refresh process on receiving a first command. The first refresh process includes reprogramming at least one second memory cell among first memory cells to which data has been programmed in a first group. In executing the first refresh process, the controller is configured to: select the second memory cell by verifying with a first voltage using a first amount in a case where the second memory cell has been programmed using the first voltage; and select the second memory cell by verifying with a second voltage using a second amount in a case where the second memory cell has been programmed using the second voltage.

Abstract: According to one embodiment, a memory system includes a memory and a controller electrically connected to the memory. The memory includes blocks. Each of the blocks includes one or more sub-blocks. Each of the one or more sub-blocks includes nonvolatile memory cells. The controller is configured to obtain read frequency of at least one of the sub-blocks, and move data stored in the at least one of the sub-blocks so that data having substantially the same read frequency are written into one block.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The memory includes a memory cell array. The controller is configured to control a transfer phase in which a command, an address, and first data are transferred to the memory, and a program phase in which the first data is programmed into the memory cell array by the memory after the transfer phase. The controller is configured to suspend the transfer phase after initiating the transfer phase before completion of the transfer phase, then read second data from the memory, and resume the transfer phase after reading of the second data is completed.

Abstract: According to one embodiment, a nonvolatile memory includes: a memory cell array including memory cells; and a controller configured to execute a first refresh process on receiving a first command. The first refresh process includes reprogramming at least one second memory cell among first memory cells to which data has been programmed in a first group. In executing the first refresh process, the controller is configured to: select the second memory cell by verifying with a first voltage using a first amount in a case where the second memory cell has been programmed using the first voltage; and select the second memory cell by verifying with a second voltage using a second amount in a case where the second memory cell has been programmed using the second voltage.

Abstract: A memory system includes a non-volatile memory chip that includes a memory cell array, and a memory controller. The memory controller is configured to perform a read operation on the non-volatile memory chip by instructing the non-volatile memory chip to perform a sensing operation to read data stored in the memory cell array, estimating a time when the read data becomes ready to be transferred from the non-volatile memory chip to the memory controller, and instructing the non-volatile memory chip, after the estimated time, to perform a transfer operation to transfer the read data to the memory controller.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller that controls operation of the nonvolatile memory. The nonvolatile memory is configured to receive, from the memory controller, a first command for execution of at least one of an erase operation and a program operation; in response to receiving a second command from the memory controller during execution of a first operation requested by the first command, execute a second operation for suspending the first operation before the first operation reaches a given section; and in response to receiving a third command from the memory controller during the execution of the first operation, suspend the first operation after the given section.

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The memory includes a memory cell array. The controller is configured to control a transfer phase in which a command, an address, and first data are transferred to the memory, and a program phase in which the first data is programmed into the memory cell array by the memory after the transfer phase. The controller is configured to suspend the transfer phase after initiating the transfer phase before completion of the transfer phase, then read second data from the memory, and resume the transfer phase after reading of the second data is completed.

Abstract: According to one embodiment, a controller of a host causes a memory device to transit from a first state that is an active state to a second state that is a sleep state in a case where there is no access to the memory device for a first time or more. The controller causes the memory device to transit from the second state to the first state in a case where there is no access to the memory device for a second time or more after the transition to the second state.

Abstract: According to one embodiment, a memory system includes a first memory as a nonvolatile memory storing first data, second data as a translation table for accessing the first data, third data, fourth data as a translation table for accessing the third data, and including two memory cell arrays which are accessible in parallel, a second memory in which the second and fourth data is storable, and which stores a management table for managing information about whether the second and fourth data is stored in the second memory, a controller checking whether the second and fourth data is stored in the second memory based on the management table, a third memory storing an order of executing commands to be issued to the first memory, and a scheduler scheduling the order based on a result of the checking, two of a first command for reading the first data, a second command for reading the second data, a third command for reading the third data and a fourth command for reading the fourth data being executed in parallel in t

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.

Abstract: According to one embodiment, a nonvolatile memory includes: a memory cell array including memory cells; and a controller configured to execute a first refresh process on receiving a first command. The first refresh process includes reprogramming at least one second memory cell among first memory cells to which data has been programmed in a first group. In executing the first refresh process, the controller is configured to: select the second memory cell by verifying with a first voltage using a first amount in a case where the second memory cell has been programmed using the first voltage; and select the second memory cell by verifying with a second voltage using a second amount in a case where the second memory cell has been programmed using the second voltage.