Patents by Inventor Riki SUZUKI
Riki SUZUKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10545691Abstract: According to one embodiment, a controller executes first refreshing in a case where a first value of a first block is larger than a first threshold and less than a second threshold. The first refreshing includes reprogramming a plurality of second memory cells among a plurality of first memory cells included in the first block.Type: GrantFiled: June 19, 2018Date of Patent: January 28, 2020Assignee: Toshiba Memory CorporationInventors: Riki Suzuki, Toshikatsu Hida, Tokumasa Hara
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Patent number: 10529730Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.Type: GrantFiled: August 1, 2018Date of Patent: January 7, 2020Assignee: Toshiba Memory CorporationInventors: Takehiko Amaki, Yoshihisa Kojima, Toshikatsu Hida, Marie Grace Izabelle Angeles Sia, Riki Suzuki, Shohei Asami
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Patent number: 10521129Abstract: According to one embodiment, a memory system includes a first memory as a nonvolatile memory storing first data, second data as a translation table for accessing the first data, third data, fourth data as a translation table for accessing the third data, and including two memory cell arrays which are accessible in parallel, a second memory in which the second and fourth data is storable, and which stores a management table for managing information about whether the second and fourth data is stored in the second memory, a controller checking whether the second and fourth data is stored in the second memory based on the management table, a third memory storing an order of executing commands to be issued to the first memory, and a scheduler scheduling the order based on a result of the checking, two of a first command for reading the first data, a second command for reading the second data, a third command for reading the third data and a fourth command for reading the fourth data being executed in parallel in tType: GrantFiled: November 26, 2018Date of Patent: December 31, 2019Assignee: Toshiba Memory CorporationInventors: Sayano Aga, Toshikatsu Hida, Riki Suzuki
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Patent number: 10475518Abstract: According to one embodiment, a memory system comprises a nonvolatile memory, and a memory controller configured to manage a history value about setting of a read voltage in performing reading of data from the nonvolatile memory, in accordance with a first management unit and a second management unit, a size of the second management unit being smaller than a size of the first management unit. A first region of the nonvolatile memory corresponds to the first management unit. A plurality of second regions of the nonvolatile memory each correspond to the second management unit. The first region includes the plurality of second regions.Type: GrantFiled: October 22, 2018Date of Patent: November 12, 2019Assignee: Toshiba Memory CorporationInventors: Takehiko Amaki, Riki Suzuki, Yoshihisa Kojima
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Publication number: 20190332285Abstract: A memory system includes a nonvolatile semiconductor memory including a first memory region for storing start-up information and a second memory region for storing a copy of the start-up information, a volatile semiconductor memory, and a controller. The controller is configured to determine whether or not an address of the second memory region is stored in the volatile semiconductor memory, issue a first start-up read command, which designates no read address, to the nonvolatile semiconductor memory to read the start-up information from the first memory region if the address of the second memory region is not stored in the volatile semiconductor memory, and issue a second start-up read command, which designates the address of the second memory region as a read address, to read the start-up information from the second memory region if the address of the second memory region is stored in the volatile semiconductor memory.Type: ApplicationFiled: July 9, 2019Publication date: October 31, 2019Inventors: Riki SUZUKI, Toshikatsu HIDA, Takehiko AMAKI, Shunichi IGAHARA
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Patent number: 10437490Abstract: A memory system includes a nonvolatile semiconductor memory including a first memory region for storing start-up information and a second memory region for storing a copy of the start-up information, a volatile semiconductor memory, and a controller. The controller is configured to determine whether or not an address of the second memory region is stored in the volatile semiconductor memory, issue a first start-up read command, which designates no read address, to the nonvolatile semiconductor memory to read the start-up information from the first memory region if the address of the second memory region is not stored in the volatile semiconductor memory, and issue a second start-up read command, which designates the address of the second memory region as a read address, to read the start-up information from the second memory region if the address of the second memory region is stored in the volatile semiconductor memory.Type: GrantFiled: October 18, 2017Date of Patent: October 8, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Riki Suzuki, Toshikatsu Hida, Takehiko Amaki, Shunichi Igahara
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Patent number: 10432231Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.Type: GrantFiled: November 2, 2016Date of Patent: October 1, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Riki Suzuki, Toshikatsu Hida, Osamu Torii, Hiroshi Yao, Kiyotaka Iwasaki
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Publication number: 20190295658Abstract: According to one embodiment, a memory system comprises a nonvolatile memory, and a memory controller configured to manage a history value about setting of a read voltage in performing reading of data from the nonvolatile memory, in accordance with a first management unit and a second management unit, a size of the second management unit being smaller than a size of the first management unit. A first region of the nonvolatile memory corresponds to the first management unit. A plurality of second regions of the nonvolatile memory each correspond to the second management unit. The first region includes the plurality of second regions.Type: ApplicationFiled: October 22, 2018Publication date: September 26, 2019Applicant: Toshiba Memory CorporationInventors: Takehiko AMAKI, Riki Suzuki, Yoshihisa Kojima
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Publication number: 20190294358Abstract: According to one embodiment, a memory system includes a memory and a controller electrically connected to the memory. The memory includes blocks. Each of the blocks includes one or more sub-blocks. Each of the one or more sub-blocks includes nonvolatile memory cells. The controller is configured to obtain read frequency of at least one of the sub-blocks, and move data stored in the at least one of the sub-blocks so that data having substantially the same read frequency are written into one block.Type: ApplicationFiled: December 7, 2018Publication date: September 26, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Riki Suzuki, Yoshihisa Kojima, Toshikatsu Hida
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Publication number: 20190273516Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.Type: ApplicationFiled: May 22, 2019Publication date: September 5, 2019Applicant: Toshiba Memory CorporationInventors: Riki SUZUKI, Toshikatsu Hida, Osamu Torii, Hiroshi Yao, Kiyotaka Iwasaki
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Publication number: 20190096487Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.Type: ApplicationFiled: September 12, 2018Publication date: March 28, 2019Applicant: Toshiba Memory CorporationInventors: Suguru NISHIKAWA, Yoshihisa Kojima, Riki Suzuki, Masanobu Shirakawa, Toshikatsu Hida
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Publication number: 20190095116Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.Type: ApplicationFiled: August 30, 2018Publication date: March 28, 2019Applicant: Toshiba Memory CorporationInventors: Shunichi Igahara, Toshikatsu Hida, Riki Suzuki, Takehiko Amaki, Suguru Nishikawa, Yoshihisa Kojima
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Publication number: 20190095108Abstract: According to one embodiment, a memory system includes a first memory as a nonvolatile memory storing first data, second data as a translation table for accessing the first data, third data, fourth data as a translation table for accessing the third data, and including two memory cell arrays which are accessible in parallel, a second memory in which the second and fourth data is storable, and which stores a management table for managing information about whether the second and fourth data is stored in the second memory, a controller checking whether the second and fourth data is stored in the second memory based on the management table, a third memory storing an order of executing commands to be issued to the first memory, and a scheduler scheduling the order based on a result of the checking, two of a first command for reading the first data, a second command for reading the second data, a third command for reading the third data and a fourth command for reading the fourth data being executed in parallel in tType: ApplicationFiled: November 26, 2018Publication date: March 28, 2019Applicant: Toshiba Memory CorporationInventors: Sayano AGA, Toshikatsu HIDA, Riki SUZUKI
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Publication number: 20190087101Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The memory includes a memory cell array. The controller is configured to control a transfer phase in which a command, an address, and first data are transferred to the memory, and a program phase in which the first data is programmed into the memory cell array by the memory after the transfer phase. The controller is configured to suspend the transfer phase after initiating the transfer phase before completion of the transfer phase, then read second data from the memory, and resume the transfer phase after reading of the second data is completed.Type: ApplicationFiled: September 7, 2018Publication date: March 21, 2019Applicant: Toshiba Memory CorporationInventors: Shizuka ENDO, Riki SUZUKI, Yoshihisa KOJIMA
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Publication number: 20190074283Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.Type: ApplicationFiled: August 1, 2018Publication date: March 7, 2019Applicant: Toshiba Memory CorporationInventors: Takehiko AMAKI, Yoshihisa Kojima, Toshikatsu Hida, Marie Sia, Riki Suzuki, Shohei Asami
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Patent number: 10175889Abstract: According to one embodiment, a memory system includes a first memory as a nonvolatile memory storing first data, second data as a translation table for accessing the first data, third data, fourth data as a translation table for accessing the third data, and including two memory cell arrays which are accessible in parallel, a second memory in which the second and fourth data is storable, and which stores a management table for managing information about whether the second and fourth data is stored in the second memory, a controller checking whether the second and fourth data is stored in the second memory based on the management table, a third memory storing an order of executing commands to be issued to the first memory, and a scheduler scheduling the order based on a result of the checking, two of a first command for reading the first data, a second command for reading the second data, a third command for reading the third data and a fourth command for reading the fourth data being executed in parallel in tType: GrantFiled: September 13, 2016Date of Patent: January 8, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Sayano Aga, Toshikatsu Hida, Riki Suzuki
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Publication number: 20180300071Abstract: According to one embodiment, a controller executes first refreshing in a case where a first value of a first block is larger than a first threshold and less than a second threshold. The first refreshing includes reprogramming a plurality of second memory cells among a plurality of first memory cells included in the first block.Type: ApplicationFiled: June 19, 2018Publication date: October 18, 2018Applicant: Toshiba Memory CorporationInventors: Riki SUZUKI, Toshikatsu HIDA, Tokumasa HARA
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Patent number: 10025514Abstract: According to one embodiment, a controller executes first refreshing in a case where a first value of a first block is larger than a first threshold and less than a second threshold. The first refreshing includes reprogramming a plurality of second memory cells among a plurality of first memory cells included in the first block.Type: GrantFiled: April 7, 2017Date of Patent: July 17, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Riki Suzuki, Toshikatsu Hida, Tokumasa Hara
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Publication number: 20180107413Abstract: A memory system includes a nonvolatile semiconductor memory including a first memory region for storing start-up information and a second memory region for storing a copy of the start-up information, a volatile semiconductor memory, and a controller. The controller is configured to determine whether or not an address of the second memory region is stored in the volatile semiconductor memory, issue a first start-up read command, which designates no read address, to the nonvolatile semiconductor memory to read the start-up information from the first memory region if the address of the second memory region is not stored in the volatile semiconductor memory, and issue a second start-up read command, which designates the address of the second memory region as a read address, to read the start-up information from the second memory region if the address of the second memory region is stored in the volatile semiconductor memory.Type: ApplicationFiled: October 18, 2017Publication date: April 19, 2018Inventors: Riki SUZUKI, Toshikatsu HIDA, Takehiko AMAKI, Shunichi IGAHARA
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Patent number: 9891848Abstract: According to one embodiment, a nonvolatile memory system includes a memory including a first memory and a second memory, the first memory including memory strings, the memory strings including memory cell transistors connected in series; and a memory controller which compresses a failure string position information of the first memory, which stores the compressed failure string position information in the second memory, and which decompresses the compressed failure string position information stored in the second memory.Type: GrantFiled: September 8, 2015Date of Patent: February 13, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shohei Asami, Tokumasa Hara, Hiroshi Yao, Kenichiro Yoshii, Riki Suzuki, Toshikatsu Hida, Osamu Torii