Abstract: Embodiments of the present disclosure provide methods and apparatuses related to programming multilevel memory cells of a memory device. Other embodiments may be described and claimed.

Abstract: A nonvolatile memory controller to recover encoded data by performing a hard-decision inner error correction code decoding and an outer error correction code decoding of the data decoded using the hard-decision inner error correction code decoding and then determining if the encoded data has been successfully decoded. If the encoded data has not been successfully decoded, the controller performs a soft-decision inner error correction code decoding of the encoded data using a soft-decision algorithm and an outer error correction code decoding of the data decoded using the soft-decision inner error correction code decoding and then determining if the encoded data has been successfully decoded. If the encoded data has not been successfully decoded, the controller recovers the data by performing a RAID operation on the encoded data.

Abstract: A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory. The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device. This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.

Abstract: Methods and apparatus for programming a memory include programming cells to a first threshold voltage, verifying programming using a first verify voltage, and applying a test read voltage to verify again that the cells are programmed to the first threshold voltage. The test read voltage is lower than the first verify voltage.

Abstract: In various embodiments, a data correction system has a data path including search modules. Each of the search modules has a respective bit error capacity for locating a number of data bit errors in a data unit based on a locator polynomial. The data correction system generates a syndrome based on an input data unit, generates a locator polynomial based on the syndrome, and determines a number of data bit errors in the input data unit based on the locator polynomial. Additionally, the data correction system selects one of the search modules having a bit error capacity of at least the number of data bit errors in the input data unit. The selected search module generates an error indicator based on the locator polynomial. The data correction system corrects each data bit error in the input data unit based on the error indicator.

Abstract: A reading method for a memory device with error-correcting encoding envisages the steps of: carrying out a first reading of a plurality of memory locations (A0, A1, . . . , ALS-1) to generate a first recovered string (S1), and performing a first decoding attempt using the first recovered string (S1). When the first decoding attempt fails, the memory locations are read at least one second time, and at least one second recovered string (S2-SN) is generated. On the basis of a comparison between the first recovered string (S1) and the second recovered string (S2-SN), a modified string (SM) is generated, in which erasures (X) are located, and at least one second decoding attempt is carried out using the modified string (SM).

Abstract: A solid state mass storage device having a first storage area portion and a second storage area portion. The mass storage device including accessing means adapted to cause data to be stored in the first storage area portion in one of: only in memory cells belonging to columns of a first collection or only to columns of a second collection such that memory cells of the first storage area portion belonging to the first or second collection are left unprogrammed; or only in memory cells of even rows or only memory cells of odd row such that the memory cells of the first storage area belonging to the even or to the odd rows are left unprogrammed; or only in memory cells such that memory cells that are immediately adjacent to said memory cells in said row and column are left unprogrammed.

Abstract: A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory. The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device. This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.

Abstract: A reading method for a memory device with error-correcting encoding envisages the steps of: carrying out a first reading of a plurality of memory locations (A0, A1, . . . , ALS-1) to generate a first recovered string (S1), and performing a first decoding attempt using the first recovered string (S1). When the first decoding attempt fails, the memory locations are read at least one second time, and at least one second recovered string (S2-SN) is generated, On the basis of a comparison between the first recovered string (S1) and the second recovered string (S2-SN), a modified string (SM) is generated, in which erasures (X) are located, and at least one second decoding attempt is carried out using the modified string (SM).

Abstract: A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.

Abstract: A reading method for a memory device with error-correcting encoding envisages the steps of: carrying out a first reading of a plurality of memory locations (A0, A1, . . . , ALS?1) to generate a first recovered string (S1), and performing a first decoding attempt using the first recovered string (S1). When the first decoding attempt fails, the memory locations are read at least one second time, and at least one second recovered string (S2-SN) is generated. On the basis of a comparison between the first recovered string (S1) and the second recovered string (S2-SN), a modified string (SM) is generated, in which erasures (X) are located, and at least one second decoding attempt is carried out using the modified string (SM).

Abstract: A circuit comprises at least one memory cell adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator is provided for generating a voltage to be supplied to the at least one memory cell for retrieving the data stored therein, the voltage generator including first means adapted to cause the generated voltage take a value in a set of target values including at least one target value, corresponding to an operation to be performed on the memory cell. The voltage generator comprises second means for causing the value taken by the generated voltage vary with temperature according to a prescribed second variation law exploiting a compensation circuit element having said electrical characteristic.

Abstract: A multistage circuit for regulating the charge voltage or the discharge current of a capacitance of an integrated device at a certain charge-pump generated boosted voltage is implemented without integrating high voltage transistor structures having a type of conductivity corresponding to the same sign of the boosted voltage (high-side transistors). The multistage circuit current includes at least a first stage, and an output stage in cascade to the first stage and coupled to the capacitance. The first stage is supplied at an unboosted power supply voltage of the integrated device, and the output stage is supplied at an unregulated charge-pump generated boosted voltage. The first stage includes a transistor having a type of conductivity corresponding to an opposite sign of the boosted voltage and of the power supply voltage. The drain of the output stage transistor is coupled to the boosted voltage either through a resistive pull-up or a voltage limiter.

Abstract: A voltage regulator integrated in a chip of semiconductor material is provided.

Abstract: An embodiment of the present invention relates to an integrated memory system comprising at least a non-volatile memory and an automatic storage error corrector, and wherein the memory is connected to a controller by means of an interface bus. Advantageously, the system comprises in the memory circuit means, functionally independent, each being responsible for the correction of a predetermined storage error; at least one of said means generating a signal to ask a correction being external to the memory.

Abstract: The capacitive coupling between two adjacent bitlines of a NAND memory device may be exploited for boosting the voltage of bitlines that are not to be programmed in order to inhibit program operations on them. The even (odd) bitlines that include cells not to be programmed are biased with a first voltage for inhibiting them from being programmed while the even (odd) bitlines that include cells to be programmed are grounded. The adjacent odd (even) bitlines are biased at the supply voltage or at an auxiliary voltage for boosting the bias voltage of the even (odd) bitlines above the supply voltage. The bias voltage of the even (odd) bitlines that include cells not to be programmed is boosted because of the relevant parasitic coupling capacitances between adjacent bitlines.

Abstract: Embodiments of the present disclosure provide methods and apparatuses related to programming multilevel memory cells of a memory device. Other embodiments may be described and claimed.

Abstract: A page buffer for an electrically programmable memory is provided. The page buffer includes a plurality of memory cells, a plurality of distinct programming states defined for each memory cell, corresponding to a number N>=2 of data bits storable in each memory cell, wherein the data bits include at least a first data bits group and a second data bits group and at least one read/program unit having a coupling line operatively associable with selected memory cells.

Abstract: A circuit comprises at least one memory cell adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator is provided for generating a voltage to be supplied to the at least one memory cell for retrieving the data stored therein, the voltage generator including first means adapted to cause the generated voltage take a value in a set of target values including at least one target value, corresponding to an operation to be performed on the memory cell. The voltage generator comprises second means for causing the value taken by the generated voltage vary with temperature according to a prescribed second variation law exploiting a compensation circuit element having said electrical characteristic.

Abstract: A level shifter is proposed.