Abstract: The capacitive coupling between two adjacent bitlines of a NAND memory device may be exploited for boosting the voltage of bitlines that are not to be programmed in order to inhibit program operations on them. The even (odd) bitlines that include cells not to be programmed are biased with a first voltage for inhibiting them from being programmed while the even (odd) bitlines that include cells to be programmed are grounded. The adjacent odd (even) bitlines are biased at the supply voltage or at an auxiliary voltage for boosting the bias voltage of the even (odd) bitlines above the supply voltage. The bias voltage of the even (odd) bitlines that include cells not to be programmed is boosted because of the relevant parasitic coupling capacitances between adjacent bitlines.

Abstract: A method for operating a flash memory device. The memory device includes a matrix of memory cells each one having a programmable threshold voltage defining a value stored in the memory cell. The method includes the steps of erasing a block of memory cells, and compacting the threshold voltages of the memory cells of the block within a predefined compacting range, wherein the step of compacting includes: selecting at least one first memory cell of the block for writing a target value; restoring the threshold voltage of a subset of the memory cells of the block to the compacting range, the subset including the at least one first memory cell and/or at least one second memory cell of the block being adjacent to the at least one first memory cell; and at least partially writing the target value into the at least one first memory cell.

Abstract: A solid-state mass storage device is provided. The solid-state mass storage device defines a storage area adapted to store data; the storage area is adapted to be exploited for storing data with a first storage density at a first data transfer speed. The storage area includes at least a first storage area portion and a second storage area portion. The solid-state mass storage device further includes accessing logic adapted to exploit the first storage area portion for storing data with a second storage density at a second data transfer speed, and adapted to exploit the second storage area portion for storing data with a third storage density and a third data transfer speed. The second storage density is lower than the third storage density, which is in turn lower than or equal to the first storage density; the second data transfer speed is higher than the third data transfer speed, which is in turn higher than or equal to the first data transfer speed.

Abstract: A page buffer for an electrically programmable memory including at least one read/program unit having a coupling line operatively associable with at least one of said bit lines and adapted to at least temporarily storing data bits read from or to be written into either one of the first or second memory page stored in the memory cells of a selected memory cell sets. The read/program unit includes enabling means for selectively enabling a change in programming state of a selected memory cell by causing the coupling line to take one among a program enabling potential and a program inhibition potential, conditioned to a target data value to be stored in the first group of data bits of the selected memory cell and an existing data value already stored in the second group of data bits of the selected memory cell.

Abstract: A method and system for making error corrections on digital information coded as symbol sequences, for example digital information stored in electronic memory systems or transmitted from and to these systems is described, provides the transmission of sequences incorporating a portion of error corrector code allowing the sequence which is more probably the original transmitted through the calculation of an error syndrome using a parity matrix to be restored when received. Advantageously according to embodiments of the invention, the error code incorporated in the original sequence belongs to a non Boolean group.

Abstract: An embodiment of an electronic apparatus is provided. The electronic apparatus includes a supplying block for supplying a plurality of operative voltages, one or more operative circuits and a distribution bus for distributing at least part of the operative voltages to each operative circuit. Each operative circuit includes a set of devices for generating a set of output voltages from a set of input ones of the distributed operative voltages. The input and output voltages span an effective range. Each device is capable of sustaining at most a safe voltage between each pair of terminals thereof not higher than the effective range. The devices are controlled by a set of auxiliary ones of the distributed operative voltages spanning an auxiliary range within the effective range, so that a difference between the voltage applied to each pair of terminals thereof is not higher than the safe voltage.

Abstract: A method of electrically programming a memory cell includes: applying at least one electrical programming pulse to the memory cell; verifying the reaching of a target programming state by the memory cell; and repeating the acts of applying and verifying until the reaching of a target programming state by the memory cell is assessed. After the reaching of a target programming state by the memory cells is assessed, at least one further electrical programming pulse is applied thereto, and the memory cell is verified at least one more time after applying the further programming pulse. In case, as a result of said further verifying, the reaching of the target programming state by the memory cell is not assessed, the method provides for applying a still further programming pulse to the memory cell.

Abstract: A column decoding system (140, 150) for selectively biasing bit lines (BLij) of a non-volatile memory device (100) is disclosed. The bit lines are logically grouped into at least one packet (PBL). For each packet, the column decoding system includes a plurality of selection paths each one for applying a biasing voltage (PEN) to a corresponding bit line, each path including a plurality of series-connected selection transistors (Mi, Mij, Pij) each one having a threshold voltage, and selection means for selecting a path corresponding to a selected bit line, the selection means including means for biasing at least one transistor in each non-selected path to an open condition to have the corresponding non-selected bit line floating; the selection means further includes means for biasing at least one other transistor in each non-selected path to a drop condition to introduce a voltage drop in the non-selected path higher than the threshold voltage of the other transistor in absolute value.

Abstract: A level shifter is proposed.

Abstract: A reading method for a memory device with error-correcting encoding envisages the steps of: carrying out a first reading of a plurality of memory locations (A0, A1, . . . , ALS?1) to generate a first recovered string (S1), and performing a first decoding attempt using the first recovered string (S1). When the first decoding attempt fails, the memory locations are read at least one second time, and at least one second recovered string (S2-SN) is generated. On the basis of a comparison between the first recovered string (S1) and the second recovered string (S2-SN), a modified string (SM) is generated, in which erasures (X) are located, and at least one second decoding attempt is carried out using the modified string (SM).

Abstract: A row selector for a semiconductor memory including a plurality of memory cells coupled to a corresponding plurality of word lines, the row selector comprising, for each word line: a first biasing circuit path adapted to bias the corresponding word line to a programming voltage when said corresponding word line is selected for selectively performing a program operation on at least one memory cell coupled to the corresponding word line, the first biasing circuit path comprising programming voltage provisioning means adapted to provide the programming voltage; a second biasing circuit path which is adapted to receive, from program-inhibit voltage provisioning means a program inhibit voltage, and to provide to the corresponding word line said program inhibit voltage when the word line is unselected during the program operation, first biasing means for driving the second biasing circuit path in order to control a conduction state thereof; wherein: said first biasing circuit path includes a first transistor contro

Abstract: A semiconductor memory device is provided that includes memory cells, sense amplifiers, signal lines, isolating circuits, and a precharging circuit. Each signal line is coupled to an output of at least one of the sense amplifiers and each of the isolating circuits isolates an associated signal line from the output of the corresponding sense amplifier at least during an evaluating phase of the datum stored in the memory cell. The signal lines include at least two groups of signal lines, arranged such that coupling capacitances between the lines of the first group and the lines of the second group are substantially negligible. The precharging circuit precharges the first group of signal lines to a first voltage level and the second group of signal lines to a second voltage level.

Abstract: A charge pump circuit includes capacitors and a number of forcing circuits for forcing the voltages on various nodes of the charge pump. The forcing circuits ensure that voltage differences across components thereof are up-limited in absolute value by a predetermined maximum voltage equal to a multiple of the absolute value of the difference between developed forcing voltages and lower than an absolute value of a charge pump voltage. The first and second forcing circuits ensure that the voltage differences across components in the forcing circuits are not higher than the predetermined maximum voltage when at least one among the voltages changes to a voltage higher in absolute value than said predetermined maximum voltage.

Abstract: A multistage circuit for regulating the charge voltage or the discharge current of a capacitance of an integrated device at a certain charge-pump generated boosted voltage is implemented without integrating high voltage transistor structures having a type of conductivity corresponding to the same sign of the boosted voltage (high-side transistors). The multistage circuit current includes at least a first stage, and an output stage in cascade to the first stage and coupled to the capacitance. The first stage is supplied at an unboosted power supply voltage of the integrated device, and the output stage is supplied at an unregulated charge-pump generated boosted voltage. The first stage includes a transistor having a type of conductivity corresponding to an opposite sign of the boosted voltage and of the power supply voltage. The drain of the output stage transistor is coupled to the boosted voltage either through a resistive pull-up or a voltage limiter.

Abstract: A trimming structure for trimming functional parameters of an Integrated Circuit—IC—(100) includes a first (115a) and at least one second functional blocks (115b, . . . ,115n) with which a first (Vrg,a) and at least one second IC functional parameters (Vrg,b, . . . ,Vrg,n) are respectively associated. The trimming structure includes respective trimmable circuit structures (205a,210a, . . . ,205n,210n) included in the first and at least one second functional blocks, and trimming configuration storage (110) for storing trimming configurations for the trimmable circuit structures. A change in the trimming configuration of the first functional block causes a corresponding change in the trimming configuration of the second functional block.

Abstract: A memory system comprising a semiconductor memory for storing digital data, said memory being connectable to a control device in order to receive an address signal and to make data selected through the output-available address signal. The system is characterised in that it comprises a generating circuit for activating a wait signal to be forwarded to the control device during reading operations in such a way as to indicate the non-availability of the data to be read. The generating circuit is such to deactivate the wait signal, in such a way as to indicate the availability of the data to be read, following a waiting time interval correlated with an effective access time for said memory.

Abstract: Voltage-boosting device having a supply input receiving a supply voltage, and a high-voltage output. The device is formed by a plurality of charge-pump stages series-connected between the supply input and the high-voltage output. Each charge-pump stage has a respective enabling input receiving an enabling signal. A control circuit formed by a plurality of comparators is connected to the high-voltage output and generates the enabling signals on the basis of the comparison between the voltage on the high-voltage output and a plurality of reference voltages, one for each comparator. The charge-pump stages are grouped into sets of stages, and the stages belonging to a same set receive a same enabling signal; thus, as many comparators as there are sets of stages are present.

Abstract: A high-voltage switch has a high-voltage input terminal, receiving a high voltage, and an output terminal. A pass transistor, having a control terminal, is connected between the high-voltage input terminal and the output terminal. The output of a voltage-multiplying circuit of the charge-pump type is connected to the control terminal. The voltage-multiplying circuit is of a symmetrical type, has first and second charge-storage means, receiving a clock signal of a periodic type, and has a first circuit branch and a second circuit branch, which are symmetrical to one another and operate in phase opposition with respect to the clock signal.

Abstract: Multi-level programming allows for writing a first and a second bit in selected cells by separately programming the first bit from the second bit. Programming of the first bit determines a shifting from a first threshold level to a second threshold level. Programming of the second bit requires a preliminary reading to detect whether the first bit has been modified, performing a first writing step to bring the cell to a third threshold voltage if the first bit has been modified and performing a second writing step to bring the selected cell to a fourth threshold voltage different from the third threshold level if the first bit has not been modified. For increasing reading and program reliability, during preliminary reading of the second portion a reading result is forced to correspond to the first threshold level.

Abstract: A reading method of a NAND memory device includes the steps of first connecting a first end terminal of a stack of cells to a reference line, second connecting a second end terminal of the stack of cells to a respective bitline, and charging the bitline to a predetermined bitline read voltage, where one of the steps of first connecting and second connecting is carried out before charging the bitline and the other of the steps of first connecting and second connecting is carried out after charging the bitline. An order of carrying out the steps of first connecting and second connecting is determined based on an address of a selected cell.