Abstract: A method for correcting errors in multilevel memories, both of the NAND and of the NOR type provides the use of a BCH correction code made parallel by means of a coding and decoding architecture allowing the latency limits of prior art sequential solutions to be overcome. The method provides a processing with a first predetermined parallelism for the coding step, a processing with a second predetermined parallelism for the syndrome calculation and a processing with a third predetermined parallelism for calculating the error position, each parallelism being defined by a respective integer number being independent from the others.

Abstract: A method and system for correcting errors in multilevel memories is based upon using a combination of a BCH correction code and a Hamming correction code. The BCH correction code is used for correcting multiple errors, and the Hamming correction code is used for correcting single errors. The Hamming correction code reduces the use of the decoding blocks for the BCH correction codes, which are computationally intensive.

Abstract: A trimming structure for trimming functional parameters of an Integrated Circuit—IC—(100) includes a first (115a) and at least one second functional blocks (115b, . . . ,115n) with which a first (Vrg,a) and at least one second IC functional parameters (Vrg,b, . . . ,Vrg,n) are respectively associated. The trimming structure includes respective trimmable circuit structures (205a,210a, . . . ,205n,210n) included in the first and at least one second functional blocks, and trimming configuration storage (110) for storing trimming configurations for the trimmable circuit structures. A change in the trimming configuration of the first functional block causes a corresponding change in the trimming configuration of the second functional block.

Abstract: A circuit (115,145,150), for programming a non-volatile memory device (100) having a plurality of memory cells (105), includes a plurality of driving elements (115) each one for applying a program pulse to a selected memory cell to be programmed. The driving elements are suitable to be supplied by a power supply unit (120,125), and a control means (145,150) controls the driving elements (115). The control means (145,150) includes means (150,205) for determining a residual capacity of the power supply unit, and a selecting means (145) selectively enables the driving elements (115) according to the residual capacity. A method of programming, an integrated circuit, and a computer system are also disclosed.

Abstract: The invention relates to a method for pinpointing erase-failed memory cells and to a relevant integrated non-volatile memory device, of the programmable and electrically erasable type comprising a sectored array of memory cells arranged in rows and columns, with at least one row-decoding circuit portion per sector being supplied positive and negative voltages. This method becomes operative upon a negative erase algorithm issue, and comprises the following steps: forcing the read condition of a sector that has not been completely erased; scanning the rows of said sector to check for the presence of a spurious current indicating a failed state; finding the failed row and electrically isolating it for re-addressing the same to a redundant row provided in the same sector.

Abstract: The memory device has a memory block, formed by a plurality of standard sectors and a redundancy portion; a control circuit, which controls programming and erasing of the data of the memory cells; and a correctness verifying circuit for the data stored in the memory cells. The correctness verifying circuit is enabled by the control circuit and generates an incorrect-datum signal in the event of detection of at least one non-functioning cell. The control circuit moreover activates redundancy, enabling the redundancy portion and storing redundancy data in a redundancy-memory stage in response to detecting an incorrect datum. Various solutions implement column, row and sector redundancy, both in case of erasing and programming.

Abstract: A self-repair method intervenes at the end of an operation of modification of a nonvolatile memory, selected between programming and erasing, in the event of detection of just one non-functioning cell, and carries out redundancy of the non-functioning cell. To this end, the memory array is divided into a basic portion, formed by a plurality of memory cells storing basic data, and into an in-the-field redundancy portion. The in-the-field redundancy portion is designed to store redundancy data that include a correct content of the non-functioning cell, the address of the non-functioning cell, and an activated redundancy flag. The redundancy is activated only after applying a preset maximum number of modification pulses and uses a redundancy replacement circuit and a redundancy data verification circuit.

Abstract: The method for using a nonvolatile memory (1) having a plurality of cells (14), each of which stores a datum, is based upon the steps of performing an modification operation of erasing/programming (22) the data of the memory; verifying (23) the correctness of the data of the memory cells; and, if the step of verifying (23) has revealed at least one incorrect datum, correcting on-th-field (46) the incorrect datum, using an error correcting code. The verification (23) of the correctness of the data is performed by determining (23) the number of memory cells storing an incorrect datum; if the number of memory cells storing the incorrect datum is less than or equal to a threshold (46), the erroneous datum is corrected by the error correction code; otherwise, new erasing/programming pulses are supplied.

Abstract: A memory device includes an array of memory cells organized into a plurality of sectors, and local wordlines and local bitlines are connected to the memory cells in each respective sector. Main read wordlines and main program wordlines are connected to the local wordlines in each sector. A main read row decoder is connected to the main read wordlines, and a main program row decoder connected to the main program wordlines. Main read bitlines and main program bitlines are connected to the local bitlines in each sector. A main read column decoder is connected to the main read bitlines, and a main program column decoder is connected to the main program wordlines. A read address bus is connected to the main read row decoder and to the main read column decoder for providing an address thereto. A program address bus is connected to the main read column decoder and to the main program row decoder for providing an address thereto.

Abstract: Described herein is an erase method for an electrically erasable nonvolatile memory device, in particular an EEPROM-FLASH nonvolatile memory device, comprising a memory array formed by a plurality of memory cells arranged in rows and columns and grouped in sectors each formed by a plurality of subsectors, which are in turn formed by one or more rows. Erase of the memory array is performed by sectors and for each sector envisages applying an erase pulse to the gate terminals of all the memory cells of the sector, verifying erase of the memory cells of each subsector, and applying a further erase pulse to the gate terminals of the memory cells of only the subsectors that are not completely erased.

Abstract: A voltage booster device to selectively assume an active status and a stand-by status with a first terminal to assume a respective electric potential and associated to a first capacitor, a second terminal associated to a second capacitor and selectively connectable to the first terminal, and a discharge circuit for discharging the first capacitor thus reducing the electrical potential of the first terminal, the discharge circuit being activated when said device is in the stand-by status and the second terminal is disconnected from said first terminal.

Abstract: A power supply circuit structure is useful with a row decoder for reading/writing data from/into memory cells of an integrated electrically programmable/erasable non-volatile memory device incorporating an array of multilevel memory cells. Advantageously, multiple supply voltages to the row decoder and a switching circuit for transferring the voltages over hierarchic-mode enabled conduction paths are provided.

Abstract: A method and a circuit are for regulating the source terminal voltage of a non-volatile memory cell during the cell programming and/or reading phases. The method includes a phase of locally regulating the voltage value and includes comparing the source current of the cell array with a reference current. A fraction of the source current is converted to a voltage and compared with a voltage generated from a memory cell acting as a reference and being programmed to the distribution with the highest current levels. The comparison may be used for controlling a current generator to inject, into the source terminal, the current necessary to keep the predetermined voltage thereof at a constant value.

Abstract: An embodiment of the present invention relates to an integrated memory system comprising at least a non-volatile memory and an automatic storage error corrector, and wherein the memory is connected to a controller by means of an interface bus. Advantageously, the system comprises in the memory circuit means, functionally independent, each being responsible for the correction of a predetermined storage error; at least one of said means generating a signal to ask a correction being external to the memory.

Abstract: The invention relates to a method for pinpointing erase-failed memory cells and to a relevant integrated non-volatile memory device, of the programmable and electrically erasable type comprising a sectored array of memory cells arranged in rows and columns, with at least one row-decoding circuit portion per sector being supplied positive and negative voltages. This method becomes operative upon a negative erase algorithm issue, and comprises the following steps: forcing the read condition of a sector that has not been completely erased; scanning the rows of said sector to check for the presence of a spurious current indicating a failed state; finding the failed row and electrically isolating it for re-addressing the same to a redundant row provided in the same sector.

Abstract: A method and program-load circuit is for regulating the voltages at the drain and body terminals of a non-volatile memory cell being programmed. These voltages are applied from a program-load circuit connected in a conduction pattern to transfer a predetermined voltage value to at least one terminal of the memory cell. The method includes a step of regulating the voltage value locally, within the program-load circuit, to overcome the effect of a parasitic resistor present in the conduction pattern.

Abstract: The invention relates to a method for erasing non-volatile memory cells, and to a corresponding non-volatile memory device of the programmable and electrically erasable type implementing the method, and comprising a memory cell array organized in a row-and-column layout, and divided in array sectors, including at least one row decode circuit portion being supplied positive and negative voltages. The method is applied whenever the issue of the erase algorithm is negative, and comprises the following steps: forcing an incompletely erased sector into a read condition; scanning the rows of said sector to check for the possible presence of a spurious current indicating a fail state; identifying and electrically isolating the failed row; re-addressing from said failed row to a redundant row provided in the same sector; re-starting the erase algorithm.

Abstract: A memory system comprising a semiconductor memory for storing digital data, said memory being connectable to a control device in order to receive an address signal and to make data selected through the output-available address signal. The system is characterised in that it comprises a generating circuit for activating a wait signal to be forwarded to the control device during reading operations in such a way as to indicate the non-availability of the data to be read. The generating circuit is such to deactivate the wait signal, in such a way as to indicate the availability of the data to be read, following a waiting time interval correlated with an effective access time for said memory.

Abstract: A method for programming a nonvolatile memory cell envisages applying in succession, to the gate terminal of the memory cell, a first and a second programming pulse trains with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next in the first programming pulse train is greater than the amplitude increment between one pulse and the next in the second programming pulse train. The programming method envisages applying, to the gate terminal of the memory cell and before the first programming pulse train, a third programming pulse train with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next may be less than the amplitude increment in the first programming pulse train and substantially equal to the amplitude increment in the second programming pulse train, or else may be greater than the amplitude increment in the first programming pulse train.

Abstract: A device and method for programming an electrically programmable memory accesses a group of memory cells (MC1-MCk) of the memory to ascertain a programming state thereof (401,407;503,509a,513a); applies a programming pulse to those memory cells in the group whose programming state is not ascertained to correspond to a desired programming state (405;507a,509c,513c); and repeats the steps of accessing and applying for the memory cells in the group whose programming state is not ascertained (411;509b,513b). After the programming state of a prescribed number of memory cells in the group has been ascertained, the memory cells in the group are accessed again and the programming state of the memory cells whose programming state was previously ascertained is re-ascertained (413,415;515). At least one additional programming pulse is applied to those memory cells in the group whose programming state is not re-ascertained (405;507a,509c,513c).