Patents by Inventor Rishabh Mehandru

Rishabh Mehandru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200312846
    Abstract: An integrated circuit includes: a germanium-containing fin structure above a layer of insulation material; a group III-V semiconductor material containing fin structure above the layer of insulation material; a first gate structure on a portion of the germanium-containing fin structure; a second gate structure on a portion of the group III-V semiconductor material containing fin structure; a first S/D region above the layer of insulation material and laterally adjacent to the portion of the germanium-containing fin structure, the first S/D region comprising a p-type impurity and at least one of silicon or germanium; a second S/D region above the layer of insulation material and laterally adjacent to the portion of the group III-V semiconductor material containing fin structure, the second S/D region comprising an n-type impurity and a second group III-V semiconductor material; and a layer comprising germanium between the layer of insulation material and the second S/D region.
    Type: Application
    Filed: December 29, 2017
    Publication date: October 1, 2020
    Applicant: INTEL CORPORATION
    Inventors: Willy Rachmady, Abhishek A. Sharma, Ravi Pillarisetty, Patrick Morrow, Rishabh Mehandru, Aaron D. Lilak, Gilbert Dewey, Cheng-Ying Huang
  • Patent number: 10790281
    Abstract: Disclosed herein are stacked channel structures for metal oxide semiconductor field effect transistors (MOSFETs) and related circuit elements, computing devices, and methods. For example, a stacked channel structure may include: a semiconductor substrate having a substrate lattice constant; a fin extending away from the semiconductor substrate, the fin having an upper region and a lower region; a first transistor in the lower region, wherein the first transistor has a first channel, the first channel has a first lattice constant, and the first lattice constant is different from the substrate lattice constant; and a second transistor in the upper region, wherein the second transistor has a second channel, the second channel has a second lattice constant, and the second lattice constant is different from the substrate lattice constant.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Roza Kotlyar, Stephen M. Cea, Patrick H. Keys
  • Publication number: 20200303238
    Abstract: Embodiments herein describe techniques for a semiconductor device including a carrier wafer, and an integrated circuit (IC) formed on a device wafer bonded to the carrier wafer. The IC includes a front end layer having one or more transistors at front end of the device wafer, and a back end layer having a metal interconnect coupled to the one or more transistors. One or more gaps may be formed by removing components of the one or more transistors. Furthermore, the IC includes a capping layer at backside of the device wafer next to the front end layer of the device wafer, filling at least partially the one or more gaps of the front end layer. Moreover, the IC includes one or more air gaps formed within the one or more gaps, and between the capping layer and the back end layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 19, 2019
    Publication date: September 24, 2020
    Inventors: Ehren MANNEBACH, Aaron LILAK, Rishabh MEHANDRU, Hui Jae YOO, Patrick MORROW, Kevin LIN
  • Publication number: 20200303257
    Abstract: In an embodiment of the present disclosure, a device structure includes a fin structure, a gate on the fin structure, and a source and a drain on the fin structure, where the gate is between the source and the drain. The device structure further includes an insulator layer having a first insulator layer portion adjacent to a sidewall of the source, a second insulator layer portion adjacent to a sidewall of the drain, and a third insulator layer portion therebetween adjacent to a sidewall of the gate, and two or more stressor materials adjacent to the insulator layer. The stressor materials can be tensile or compressively stressed and may strain a channel under the gate.
    Type: Application
    Filed: January 12, 2018
    Publication date: September 24, 2020
    Applicant: Intel Corporation
    Inventors: Aaron D. Lilak, Christopher J. Jezewski, Willy Rachmady, Rishabh Mehandru, Gilbert Dewey, Anh Phan
  • Publication number: 20200303509
    Abstract: Transistor structure including deep source and/or drain semiconductor that is contacted by metallization from both a front (e.g., top) side and a back (e.g., bottom) side of transistor structure. The deep source and/or drain semiconductor may be epitaxial, following crystallinity of a channel region that may be monocrystalline A first layer of the source and/or drain semiconductor may have lower impurity doping while a second layer of the source and/or drain semiconductor may have higher impurity doping. The deep source and/or drain semiconductor may extend below the channel region and be adjacent to a sidewall of a sub-channel region such that metallization in contact with the back side of the transistor structure may pass through a thickness of the first layer of the source and/or drain semiconductor to contact the second layer of the source and/or drain semiconductor.
    Type: Application
    Filed: March 22, 2019
    Publication date: September 24, 2020
    Applicant: Intel Corporation
    Inventors: Rishabh MEHANDRU, Tahir GHANI, Stephen CEA
  • Patent number: 10784358
    Abstract: An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Rishabh Mehandru, Aaron D. Lilak, Kimin Jun
  • Publication number: 20200295127
    Abstract: Disclosed herein are stacked transistors with different crystal orientations in different device strata, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein the channel materials in at least some of the strata have different crystal orientations.
    Type: Application
    Filed: March 13, 2019
    Publication date: September 17, 2020
    Applicant: Intel Corporation
    Inventors: Ehren Mannebach, Aaron D. Lilak, Anh Phan, Cheng-Ying Huang, Gilbert W. Dewey, Patrick Morrow, Rishabh Mehandru, Roza Kotlyar, Sean T. Ma, Willy Rachmady
  • Patent number: 10770458
    Abstract: Techniques are disclosed for forming nanowire transistor architectures in which the presence of gate material between neighboring nanowires is eliminated or otherwise reduced. In some examples, neighboring nanowires can be formed sufficiently proximate one another such that their respective gate dielectric layers are either: (1) just in contact with one another (e.g., are contiguous); or (2) merged with one another to provide a single, continuous dielectric layer shared by the neighboring nanowires. In some cases, a given gate dielectric layer may be of a multi-layer configuration, having two or more constituent dielectric layers. Thus, in some examples, the gate dielectric layers of neighboring nanowires may be formed such that one or more constituent dielectric layers are either: (1) just in contact with one another (e.g., are contiguous); or (2) merged with one another to provide a single, continuous constituent dielectric layer shared by the neighboring nanowires.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Tahir Ghani, Szuya S. Liao, Seiyon Kim
  • Publication number: 20200279872
    Abstract: An apparatus is provided which comprises: a source and a drain with a semiconductor body therebetween, the source, the drain, and the semiconductor body on an insulator, a buried structure between the semiconductor body and the insulator, and a source contact coupled with the source and the buried structure, the source contact comprising metal. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: January 12, 2018
    Publication date: September 3, 2020
    Applicant: INTEL CORPORATION
    Inventors: Dipanjan BASU, Rishabh MEHANDRU, Seung Hoon SUNG
  • Publication number: 20200266218
    Abstract: Disclosed herein are stacked transistors with dielectric between channel materials, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein a dielectric material is between channel materials of adjacent strata, and the dielectric material is surrounded by a gate dielectric.
    Type: Application
    Filed: February 19, 2019
    Publication date: August 20, 2020
    Applicant: Intel Corporation
    Inventors: Aaron D. Lilak, Gilbert W. Dewey, Willy Rachmady, Rishabh Mehandru, Ehren Mannebach, Cheng-Ying Huang, Anh Phan, Patrick Morrow, Kimin Jun
  • Publication number: 20200258881
    Abstract: An integrated circuit structure includes a first semiconductor fin extending horizontally in a length direction and including a bottom portion and a top portion above the bottom portion, a bottom transistor associated with the bottom portion of the first semiconductor fin, a top transistor above the bottom transistor and associated with the top portion of the first semiconductor fin, and a first vertical diode. The first vertical diode includes: a bottom region associated with at least the bottom portion of the first semiconductor fin, the bottom region including one of n-type and p-type dopant; a top region associated with at least the top portion of the first semiconductor fin, the top region including the other of n-type and p-type dopant; a bottom terminal electrically connected to the bottom region; and a top terminal electrically connected to the top region at the top portion of the first semiconductor fin.
    Type: Application
    Filed: January 18, 2018
    Publication date: August 13, 2020
    Applicant: INTEL CORPORATION
    Inventors: Aaron D. Lilak, Patrick Morrow, Anh Phan, Cheng-Ying Huang, Rishabh Mehandru, Gilbert Dewey, Willy Rachmady
  • Publication number: 20200251502
    Abstract: An apparatus includes a first layer, a second layer under the first layer along an axis, and a metal layer between the first layer and the second layer along the axis. The first layer includes a first plurality of transistors, where a given transistor of the first plurality of transistors includes a gate region; and the second layer includes a second plurality of transistors. The metal layer includes a metal below the gate region, and the metal is within thirty nanometers (nm) of the gate region.
    Type: Application
    Filed: December 26, 2017
    Publication date: August 6, 2020
    Inventors: Aaron D. Lilak, Rishabh Mehandru, Gilbert Dewey, Willy Rachmady
  • Publication number: 20200235092
    Abstract: An integrated circuit structure includes: a top semiconductor fin extending in a length direction; a bottom semiconductor fin extending in the length direction, the bottom semiconductor fin being under and vertically aligned with the top semiconductor fin; a top gate structure in contact with a portion of the top semiconductor fin; top source and drain regions each adjacent to the portion of the top semiconductor fin; a bottom gate structure in contact with a portion of the bottom semiconductor fin; and bottom source and drain regions each adjacent to the portion of the bottom semiconductor fin. The portion of the top semiconductor fin is between the top source region and the top drain region. The portion of the bottom semiconductor fin is between the bottom source and drain regions. Heights, widths, or both the heights and widths of the portions of the top and bottom semiconductor fins are different.
    Type: Application
    Filed: January 8, 2018
    Publication date: July 23, 2020
    Applicant: INTEL CORPORATION
    Inventors: Aaron D. Lilak, Cheng-ying Huang, Gilbert Dewey, Willy Rachmady, Rishabh Mehandru
  • Publication number: 20200235013
    Abstract: Stacked finFET structures including a fin having at least a first layer of semiconductor material stacked over or under a second layer of semiconductor material. The first and second layers may include a Group IV semiconductor material layer and a Group III-V semiconductor material layer, for example. A stacked finFET may include an N-type finFET stacked over or under a P-type finFET, the two finFETs may have channel portions within the different semiconductor material layers. Channel portions of the first and second layers of semiconductor material may be coupled to separate gate electrodes that are vertically aligned. Channel portions of the first and second layers of semiconductor material may be vertically separated by subfin portions of the first and second layers. Different layers of dielectric material adjacent to the subfin portions may improve electrical isolation between the channel portions, for example as a source of fixed charge or impurity dopants.
    Type: Application
    Filed: August 24, 2017
    Publication date: July 23, 2020
    Applicant: Intel Corporation
    Inventors: Aaron Lilak, Sean Ma, Justin R. Weber, Rishabh Mehandru, Stephen M. Cea, Patrick Morrow, Patrick H. Keys
  • Publication number: 20200235134
    Abstract: Integrated circuits with stacked transistors and methods of manufacturing the same are disclosed. An example integrated circuit includes a first transistor in a first portion of the integrated circuit, and a second transistor stacked above the first transistor and in a second portion of the integrated circuit above the first portion. The integrated circuit further includes a bonding layer between the first and second vertical portions of the integrated circuit. The bonding layer includes an opening extending therethrough between the first and second vertical portions of the integrated circuit. The integrated circuit also includes a gate dielectric on an inner wall of the opening.
    Type: Application
    Filed: December 27, 2017
    Publication date: July 23, 2020
    Applicant: Intel Corporation
    Inventors: Aaron D. Lilak, Rishabh Mehandru, Gilbert Dewey, Willy Rachmady, Anh Phan
  • Publication number: 20200227558
    Abstract: Techniques and mechanisms for imposing stress on a channel region of an NMOS transistor. In an embodiment, a fin structure on a semiconductor substrate includes two source or drain regions of the transistor, wherein a channel region of the transistor is located between the source or drain regions. At least on such source or drain region includes a doped silicon germanium (SiGe) compound, wherein dislocations in the SiGe compound result in the at least one source or drain region exerting a tensile stress on the channel region. In another embodiment, source or drain regions of a transistor each include a SiGe compound which comprises at least 50 wt % germanium.
    Type: Application
    Filed: September 29, 2017
    Publication date: July 16, 2020
    Applicant: INTEL CORPORATION
    Inventors: Rishabh Mehandru, Anand Murthy, Karthik Jambunathan, Cory Bomberger
  • Publication number: 20200227556
    Abstract: Techniques and mechanisms for imposing stress on transistors using an insulator. In an embodiment, an integrated circuit device includes a fin structure on a semiconductor substrate, wherein respective structures of two transistors are variously in or on the fin structure. A recess of the IC device, located in a region between the two transistors, extends at least partially through the fin structure. An insulator in the recess imposes stresses on respective channel regions of the two transistors. In another embodiment, compressive stresses or tensile stresses are imposed on the transistors with both the insulator and a buffer layer under the fin structure.
    Type: Application
    Filed: September 29, 2017
    Publication date: July 16, 2020
    Applicant: INTEL CORPORATION
    Inventor: Rishabh Mehandru
  • Publication number: 20200219997
    Abstract: Wrap-around contact structures for semiconductor nanowires and nanoribbons, and methods of fabricating wrap-around contact structures for semiconductor nanowires and nanoribbons, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above a first portion of a semiconductor sub-fin. A gate structure surrounds a channel portion of the semiconductor nanowire. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor sub-fin, the epitaxial structure having substantially vertical sidewalls in alignment with the second portion of the semiconductor sub-fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the epitaxial structure.
    Type: Application
    Filed: January 3, 2019
    Publication date: July 9, 2020
    Inventors: Rishabh MEHANDRU, Tahir GHANI, Stephen CEA, Biswajeet GUHA
  • Publication number: 20200176482
    Abstract: Embodiments of the present invention are directed to formation of fins with different active channel heights in a tri-gate or a Fin-FET device. In an embodiment, at least two fins are formed on a front side of the substrate. A gate structure extends over a top surface and a pair of sidewalls of at least a portion of the fins. In an embodiment, the substrate is thinned to expose the bottom surface of the fins. Next, backside etching may be performed on each fin to form active channel regions. The fins may be recessed to different depths, forming active channel regions with differing heights.
    Type: Application
    Filed: February 10, 2020
    Publication date: June 4, 2020
    Inventors: Aaron D. LILAK, Patrick MORROW, Stephen M. CEA, Rishabh MEHANDRU, Cory E. WEBER
  • Publication number: 20200161298
    Abstract: Metallization structures under a semiconductor device layer. A metallization structure in alignment with semiconductor fin may be on a side of the fin opposite a gate stack. Backside and/or frontside substrate processing techniques may be employed to form such metallization structures on a bottom of a semiconductor fin or between bottom portions of two adjacent fins. Such metallization structures may accompany interconnect metallization layers that are over a gate stack, for example to increase metallization layer density for a given number of semiconductor device layers.
    Type: Application
    Filed: July 1, 2017
    Publication date: May 21, 2020
    Applicant: Intel Corporation
    Inventors: Aaron D. Lilak, Rishabh Mehandru, Patrick Morrow, Stephen M. Cea