Abstract: A logic device includes a transmission gate block configured to receive a binary input and a control input, the transmission gate block configured to provide a multi-bit output that is correlated from the binary input and in response to the control input having a first value. A state driver block is activated to drive one of a low state bit pattern or a high state bit pattern to the multi-bit output in response to the control input having a second value, which is different from the first value.

Abstract: A logic device includes a transmission gate block configured to receive a binary input and a control input, the transmission gate block configured to provide a multi-bit output that is correlated from the binary input and in response to the control input having a first value. A state driver block is activated to drive one of a low state bit pattern or a high state bit pattern to the multi-bit output in response to the control input having a second value, which is different from the first value.

Abstract: An integrated circuit containing a gate controlled voltage divider having an upper resistor on field oxide in series with a transistor switch in series with a lower resistor. A resistor drift layer is disposed under the upper resistor, and the transistor switch includes a switch drift layer adjacent to the resistor drift layer, separated by a region which prevents breakdown between the drift layers. The switch drift layer provides an extended drain or collector for the transistor switch. A sense terminal of the voltage divider is coupled to a source or emitter node of the transistor and to the lower resistor. An input terminal is coupled to the upper resistor and the resistor drift layer. A process of forming the integrated circuit containing the gate controlled voltage divider.

Abstract: An integrated circuit containing a voltage divider having an upper resistor of unsilicided gate material over field oxide around a central opening and a drift layer under the upper resistor, an input terminal coupled to an input node of the upper resistor adjacent to the central opening in the field oxide and coupled to the drift layer through the central opening, a sense terminal coupled to a sense node on the upper resistor opposite from the input node, a lower resistor with a sense node coupled to the sense terminal and a reference node, and a reference terminal coupled to the reference node. A process of forming the integrated circuit containing the voltage divider.

Abstract: A system includes control circuitry configured to provide one or more control pulses in response to a command signal, the one or more control pulses being communicated from the control circuitry to associated circuitry via a connection. A detector is configured to detect a disturbing signal that mitigates reception of the one or more control pulses via the connection. The command signal is controlled to cause the control circuitry to provide one or more additional control pulses when the disturbing signal is detected by the detector to improve a likelihood of the reception of the one or more control pulses via the connection.

Abstract: An apparatus for generating an output voltage from an input voltage is provided. The apparatus comprises a switch that receives the input voltage, an inductor that is coupled to the switch, a capacitor coupled to the inductor with the output voltage being output from a node between the inductor and the capacitor, a measuring circuit that receives and measures the input voltage, and a controller that is coupled to the switch and to the measuring circuit. Additionally, the controller receives the measured input voltage and calculates an on-time for the switch based on the measured input voltage and actuates the switch for the on-time.

Abstract: A system and method for power conversion synchronizes multiple phases at a desired phase angle difference. The power conversion involves variable frequency switching, fixed on-time and provides power factor correction. A relative measure of a phase angle difference between two phases permits each phase to be controlled to obtain the desired phase angle difference. The power conversion involves transition mode switching to help reduce switching losses. A phase angle difference detector may be provided for each phase. The various phases may have different inherent frequencies that vary with switching frequency, and are synchronized to an average frequency.

Abstract: A system and method for synchronizing an oscillator with multiple phases at a desired phase angle difference. A relative measure of a phase angle difference between two phases permits each phase to be controlled to obtain the desired phase angle difference. The various phases may have different inherent frequencies that are synchronized to a common frequency such as an average of the different frequencies.

Abstract: Apparatus within power sourcing equipment and a method for determining whether a load within a powered device coupled to the power sourcing equipment via a cable is within an acceptable resistance range. If the load is within the acceptable resistance range, a voltage source is coupled to the load. In one embodiment one recharge interval is employed during which a capacitor is charged based, at least in part, on the voltage drop across the load and one discharge interval is employed during which a capacitor is discharged based, at least in part, on the voltage drop across the load. In a second embodiment, first and second recharge and discharge intervals are employed and prior to initiation of the recharge and discharge intervals, settling time periods are provided.

Abstract: Digital and analog functionality are separated and optimized in an Ethernet port architecture to free port circuit space for additional desired functionality. A power controller and physical link controller for the port share a high speed communication link to transfer information and control instructions from one to the other. The physical link controller provides digital functionality and processing capabilities that can generate power control instructions sent to the power controller over the high speed link. The power controller provides analog functionality for controlling the power supplied to the network connection and transfers power related information to the physical link controller over the high speed communication link and receives control instructions through a digital interface. The separation of digital of analog functionality simplifies the power control circuitry, removes redundancy, and frees valuable circuit board space for other desired functionality.

Abstract: Apparatus within power sourcing equipment and a method for determining whether a load within a powered device coupled to the power sourcing equipment via a cable is within an acceptable resistance range. If the load is within the acceptable resistance range, a voltage source is coupled to the load. In one embodiment one recharge interval is employed during which a capacitor is charged based, at least in part, on the voltage drop across the load and one discharge interval is employed during which a capacitor is discharged based, at least in part, on the voltage drop across the load. In a second embodiment, first and second recharge and discharge intervals are employed and prior to initiation of the recharge and discharge intervals, settling time periods are provided.

Abstract: A system and method for synchronizing an oscillator with multiple phases at a desired phase angle difference. A relative measure of a phase angle difference between two phases permits each phase to be controlled to obtain the desired phase angle difference. The various phases may have different inherent frequencies that are synchronized to a common frequency such as an average of the different frequencies.

Abstract: A system and method for power conversion synchronizes multiple phases at a desired phase angle difference. The power conversion involves variable frequency switching, fixed on-time and provides power factor correction. A relative measure of a phase angle difference between two phases permits each phase to be controlled to obtain the desired phase angle difference. The power conversion involves transition mode switching to help reduce switching losses. A phase angle difference detector may be provided for each phase. The various phases may have different inherent frequencies that vary with switching frequency, and are synchronized to an average frequency.

Abstract: A controller associated with a network connection includes a high speed local interface and a high overhead system interface. The controller can be a power controller for a power over Ethernet application. A controller for each connection is interconnected through the high speed interface. One of the controllers is configured at an address in the high overhead system interface to permit control instructions to be directed to the interconnected controllers from the host system. The architecture avoids the high overhead and complexity associated with multiple devices on the high overhead system interface and distributes processing and thermal loads among the controllers. The controller connected to the high overhead system interface can address the other controllers simply and rapidly to obtain a distributed control system for controlling power over network connections. The architecture reduces pin count, distributes thermal loads, reduces area requirements, and provides a flexible control solution.

Abstract: Digital and analog functionality are separated and optimized in an Ethernet port architecture to free port circuit space for additional desired functionality. A power controller and physical link controller for the port share a high speed communication link to transfer information and control instructions from one to the other. The physical link controller provides digital functionality and processing capabilities that can generate power control instructions sent to the power controller over the high speed link. The power controller provides analog functionality for controlling the power supplied to the network connection and transfers power related information to the physical link controller over the high speed communication link and receives control instructions through a digital interface. The separation of digital of analog functionality simplifies the power control circuitry, removes redundancy, and frees valuable circuit board space for other desired functionality.

Abstract: Circuitry is provided for controlling the slew rate of a negative output supply. The slew rate control circuitry includes an NMOS FET, a feedback resistor connected across the drain and the gate of the NMOS FET, an input resistor connected to the gate of the NMOS FET, level shifting circuitry connected between a positive output supply voltage and the input resistor, and a bias current source connected to the gate of the NMOS FET. A negative input supply voltage is connected to the source of the NMOS FET, and the negative output supply voltage is provided across a load connected to the drain of the NMOS FET. As the positive supply voltage ramps up from 0 to +VS, the level shifter provides a voltage to the input resistor that ramps up from ?VS to 0 volts. Further, the drain voltage of the NMOS FET ramps down from 0 to ?VS, thereby providing a negative output supply voltage ?VS with a slew rate that linearly tracks the slew rate of the master positive output supply.

Abstract: Power selection circuitry that may be employed in redundant power supplies. The power selection circuitry includes a comparator, a symmetric resistor array coupled between the comparator inputs and multiple input voltage sources, a plurality of first switching elements, and control logic/drive circuitry coupled between the comparator output and the first switching elements. The first switching elements connect a selected input voltage source to a load. The comparator compares the voltage levels of the respective voltage sources, and provides a voltage indicating which one of the voltage sources is operational to the control logic/drive circuitry, which applies control signals to the first switching elements to connect the operational voltage source to the load. The symmetric resistor array and a plurality of second switching elements assure that symmetric trip voltages with hysteresis are provided to the comparator.

Abstract: Circuitry is provided for controlling the slew rate of a negative output supply. The slew rate control circuitry includes an NMOS FET, a feedback resistor connected across the drain and the gate of the NMOS FET, an input resistor connected to the gate of the NMOS FET, level shifting circuitry connected between a positive output supply voltage and the input resistor, and a bias current source connected to the gate of the NMOS FET. A negative input supply voltage is connected to the source of the NMOS FET, and the negative output supply voltage is provided across a load connected to the drain of the NMOS FET. As the positive supply voltage ramps up from 0 to +VS, the level shifter provides a voltage to the input resistor that ramps up from ?VS to 0 volts. Further, the drain voltage of the NMOS FET ramps down from 0 to ?VS, thereby providing a negative output supply voltage ?VS with a slew rate that linearly tracks the slew rate of the master positive output supply.

Abstract: Power selection circuitry that may be employed in redundant power supplies. The power selection circuitry includes a comparator, a symmetric resistor array coupled between the comparator inputs and multiple input voltage sources, a plurality of first switching elements, and control logic/drive circuitry coupled between the comparator output and the first switching elements. The first switching elements connect a selected input voltage source to a load. The comparator compares the voltage levels of the respective voltage sources, and provides a voltage indicating which one of the voltage sources is operational to the control logic/drive circuitry, which applies control signals to the first switching elements to connect the operational voltage source to the load. The symmetric resistor array and a plurality of second switching elements assure that symmetric trip voltages with hysteresis are provided to the comparator.

Abstract: A brushless DC motor controller including a track and hold circuit responsive to the voltage at the motor centertap terminal and the voltage across at least one motor winding in order to determine the position of the rotor by detecting zero crossings of the back EMF of the unenergized winding in a manner having reduced susceptibility to noise. In one embodiment, the output of the track and hold circuit is interpolated to reduce the effects of pulse width modulation noise on rotor position detection. The drive signals controlling a plurality of electronically controlled switches which effect energization of the windings are chopped in order to control the speed of the motor. In one embodiment, the switch connected to a positive voltage is chopped when the sensed back EMF is positive and the switch connected to the negative voltage is chopped when the sensed back EMF is negative.