Abstract: A system includes control circuitry configured to provide one or more control pulses in response to a command signal, the one or more control pulses being communicated from the control circuitry to associated circuitry via a connection. A detector is configured to detect a disturbing signal that mitigates reception of the one or more control pulses via the connection. The command signal is controlled to cause the control circuitry to provide one or more additional control pulses when the disturbing signal is detected by the detector to improve a likelihood of the reception of the one or more control pulses via the connection.

Abstract: A logic device includes a transmission gate block configured to receive a binary input and a control input, the transmission gate block configured to provide a multi-bit output that is correlated from the binary input and in response to the control input having a first value. A state driver block is activated to drive one of a low state bit pattern or a high state bit pattern to the multi-bit output in response to the control input having a second value, which is different from the first value.

Abstract: A logic device includes a transmission gate block configured to receive a binary input and a control input, the transmission gate block configured to provide a multi-bit output that is correlated from the binary input and in response to the control input having a first value. A state driver block is activated to drive one of a low state bit pattern or a high state bit pattern to the multi-bit output in response to the control input having a second value, which is different from the first value.

Abstract: An integrated circuit containing a gate controlled voltage divider having an upper resistor on field oxide in series with a transistor switch in series with a lower resistor. A resistor drift layer is disposed under the upper resistor, and the transistor switch includes a switch drift layer adjacent to the resistor drift layer, separated by a region which prevents breakdown between the drift layers. The switch drift layer provides an extended drain or collector for the transistor switch. A sense terminal of the voltage divider is coupled to a source or emitter node of the transistor and to the lower resistor. An input terminal is coupled to the upper resistor and the resistor drift layer. A process of forming the integrated circuit containing the gate controlled voltage divider.

Abstract: An integrated circuit containing a voltage divider having an upper resistor of unsilicided gate material over field oxide around a central opening and a drift layer under the upper resistor, an input terminal coupled to an input node of the upper resistor adjacent to the central opening in the field oxide and coupled to the drift layer through the central opening, a sense terminal coupled to a sense node on the upper resistor opposite from the input node, a lower resistor with a sense node coupled to the sense terminal and a reference node, and a reference terminal coupled to the reference node. A process of forming the integrated circuit containing the voltage divider.

Abstract: A system includes control circuitry configured to provide one or more control pulses in response to a command signal, the one or more control pulses being communicated from the control circuitry to associated circuitry via a connection. A detector is configured to detect a disturbing signal that mitigates reception of the one or more control pulses via the connection. The command signal is controlled to cause the control circuitry to provide one or more additional control pulses when the disturbing signal is detected by the detector to improve a likelihood of the reception of the one or more control pulses via the connection.

Abstract: An apparatus for generating an output voltage from an input voltage is provided. The apparatus comprises a switch that receives the input voltage, an inductor that is coupled to the switch, a capacitor coupled to the inductor with the output voltage being output from a node between the inductor and the capacitor, a measuring circuit that receives and measures the input voltage, and a controller that is coupled to the switch and to the measuring circuit. Additionally, the controller receives the measured input voltage and calculates an on-time for the switch based on the measured input voltage and actuates the switch for the on-time.

Abstract: A system and method for power conversion synchronizes multiple phases at a desired phase angle difference. The power conversion involves variable frequency switching, fixed on-time and provides power factor correction. A relative measure of a phase angle difference between two phases permits each phase to be controlled to obtain the desired phase angle difference. The power conversion involves transition mode switching to help reduce switching losses. A phase angle difference detector may be provided for each phase. The various phases may have different inherent frequencies that vary with switching frequency, and are synchronized to an average frequency.

Abstract: A system and method for synchronizing an oscillator with multiple phases at a desired phase angle difference. A relative measure of a phase angle difference between two phases permits each phase to be controlled to obtain the desired phase angle difference. The various phases may have different inherent frequencies that are synchronized to a common frequency such as an average of the different frequencies.

Abstract: Apparatus within power sourcing equipment and a method for determining whether a load within a powered device coupled to the power sourcing equipment via a cable is within an acceptable resistance range. If the load is within the acceptable resistance range, a voltage source is coupled to the load. In one embodiment one recharge interval is employed during which a capacitor is charged based, at least in part, on the voltage drop across the load and one discharge interval is employed during which a capacitor is discharged based, at least in part, on the voltage drop across the load. In a second embodiment, first and second recharge and discharge intervals are employed and prior to initiation of the recharge and discharge intervals, settling time periods are provided.

Abstract: Digital and analog functionality are separated and optimized in an Ethernet port architecture to free port circuit space for additional desired functionality. A power controller and physical link controller for the port share a high speed communication link to transfer information and control instructions from one to the other. The physical link controller provides digital functionality and processing capabilities that can generate power control instructions sent to the power controller over the high speed link. The power controller provides analog functionality for controlling the power supplied to the network connection and transfers power related information to the physical link controller over the high speed communication link and receives control instructions through a digital interface. The separation of digital of analog functionality simplifies the power control circuitry, removes redundancy, and frees valuable circuit board space for other desired functionality.

Abstract: Apparatus within power sourcing equipment and a method for determining whether a load within a powered device coupled to the power sourcing equipment via a cable is within an acceptable resistance range. If the load is within the acceptable resistance range, a voltage source is coupled to the load. In one embodiment one recharge interval is employed during which a capacitor is charged based, at least in part, on the voltage drop across the load and one discharge interval is employed during which a capacitor is discharged based, at least in part, on the voltage drop across the load. In a second embodiment, first and second recharge and discharge intervals are employed and prior to initiation of the recharge and discharge intervals, settling time periods are provided.

Abstract: A system and method for power conversion synchronizes multiple phases at a desired phase angle difference. The power conversion involves variable frequency switching, fixed on-time and provides power factor correction. A relative measure of a phase angle difference between two phases permits each phase to be controlled to obtain the desired phase angle difference. The power conversion involves transition mode switching to help reduce switching losses. A phase angle difference detector may be provided for each phase. The various phases may have different inherent frequencies that vary with switching frequency, and are synchronized to an average frequency.

Abstract: A brushless DC motor controller including a track and hold circuit responsive to the voltage at the motor centertap terminal and the voltage across at least one motor winding in order to determine the position of the rotor by detecting zero crossings of the back EMF of the unenergized winding in a manner having reduced susceptibility to noise. In one embodiment, the output of the track and hold circuit is interpolated to reduce the effects of pulse width modulation noise on rotor position detection. The drive signals controlling a plurality of electronically controlled switches which effect energization of the windings are chopped in order to control the speed of the motor. In one embodiment, the switch connected to a positive voltage is chopped when the sensed back EMF is positive and the switch connected to the negative voltage is chopped when the sensed back EMF is negative.

Abstract: A quantification of approximate entropy is determined on a set of data by comparing subsets of the data. The comparison reveals the regularity and stability of similar patterns amongst subsets of the data. The comparisons perform such that the contribution of noise to measurement of the regularity and stability is minimized. Quantitative values are assigned to measure the degree of regularity and stability. From these quantitative values a single output measure is generated indicative of the amount of patternness of the sequence of data. The calculations required to determine this approximate entropy are preferably performed within a data processing system. Numerous peripheral devices may be attached to such a data processing system. The types of data for which the approximate entropy may be calculated include any sets of data wherein the amount of patternness is sought.

Abstract: A quantification of approximate entropy is determined on a set of data by comparing subsets of the data. The comparison reveals the regularity and stability of similar patterns amongst subsets of the data. The comparisons perform such that the contribution of noise to measurement of the regularity and stability is minimized. Quantitative values are assigned to measure the degree of regularity and stability. From these quantitative values a single output measure is generated indicative of the amount of patternness of the sequence of data. The calculations required to determine this approximate entropy are preferably performed within a data processing system. Numerous peripheral devices may be attached to such a data processing system. The types of data for which the approximate entropy may be calculated include any sets of data wherein the amount of patternness is sought.

Abstract: A multi-stage digital to analog converter with increased speed and enhanced accuracy. Multiple resistor ladders are interconnected through switches with the first resistor ladder converting the most significant bits and successive ladders converting lesser significant bits. The resistance values of the resistors of each ladder are greater than those of the preceding ladders in order to minimize inaccuracies due to loading. A monolithic fabrication technique includes a common resistor biasing scheme to switch the voltage across parasitic capacitances associated with the resistors in each ladder in common mode, thereby increasing the converter speed.

Abstract: A low-voltage CMOS switching controller which utilizes PMOS and nMOS devices to control the switching of a high voltage power supply. Two pMOS devices are used as switches to control the high voltage level on an output terminal and an nMOS device is used to switch the output terminal to ground once the high voltage has been reduced to a safe level. The controller also includes circuitry which prevents both pMOS devices from being on at the same time, thereby shunting the high voltage supply to ground.

Abstract: An approximation of entropy is determined on a set of data by comparing subsets of the data. The comparison reveals the regularity and stability of similar patterns amongst subsets of the data. The comparisons perform such that the contribution of noise to measurement of the regularity and stability is minimized. Quantitative values are assigned to measure the degree of regularity and stability. From these quantitative values a single output measure is generated indicative of the amount of patternness of the sequence of data. The calculations required to determine this approximate entropy are preferably performed within a data processing system. Numerous peripheral devices may be attached to such a data processing system. The types of data for which the approximate entropy may be calculated include any sets of data wherein the amount of patternness is sought.

Abstract: An analog computational circuit, for transforming an input voltage into an output voltage or current variable according to a selected transfer function, including a plurality of current sources having a common input and a common current output. Each of the current sources is energizable in response to an input voltage as it exceeds a selected input voltage threshold associated with each of the current sources. There are means coupled to the current sources for establishing the input voltage threshold associated with each of the current sources. Also included are means coupled to each of the current sources for establishing the selected transfer function of the computational circuit. Each of the current sources is adapted to begin conducting current in response to an input voltage which exceeds its associated input voltage threshold, and to provide an attenuated output current proportional to the input voltage, the proporation established by the selected transfer function.