Abstract: A quantification of approximate entropy is determined on a set of data by comparing subsets of the data. The comparison reveals the regularity and stability of similar patterns amongst subsets of the data. The comparisons perform such that the contribution of noise to measurement of the regularity and stability is minimized. Quantitative values are assigned to measure the degree of regularity and stability. From these quantitative values a single output measure is generated indicative of the amount of patternness of the sequence of data. The calculations required to determine this approximate entropy are preferably performed within a data processing system. Numerous peripheral devices may be attached to such a data processing system. The types of data for which the approximate entropy may be calculated include any sets of data wherein the amount of patternness is sought.

Abstract: A quantification of approximate entropy is determined on a set of data by comparing subsets of the data. The comparison reveals the regularity and stability of similar patterns amongst subsets of the data. The comparisons perform such that the contribution of noise to measurement of the regularity and stability is minimized. Quantitative values are assigned to measure the degree of regularity and stability. From these quantitative values a single output measure is generated indicative of the amount of patternness of the sequence of data. The calculations required to determine this approximate entropy are preferably performed within a data processing system. Numerous peripheral devices may be attached to such a data processing system. The types of data for which the approximate entropy may be calculated include any sets of data wherein the amount of patternness is sought.

Abstract: A multi-stage digital to analog converter with increased speed and enhanced accuracy. Multiple resistor ladders are interconnected through switches with the first resistor ladder converting the most significant bits and successive ladders converting lesser significant bits. The resistance values of the resistors of each ladder are greater than those of the preceding ladders in order to minimize inaccuracies due to loading. A monolithic fabrication technique includes a common resistor biasing scheme to switch the voltage across parasitic capacitances associated with the resistors in each ladder in common mode, thereby increasing the converter speed.

Abstract: A low-voltage CMOS switching controller which utilizes PMOS and nMOS devices to control the switching of a high voltage power supply. Two pMOS devices are used as switches to control the high voltage level on an output terminal and an nMOS device is used to switch the output terminal to ground once the high voltage has been reduced to a safe level. The controller also includes circuitry which prevents both pMOS devices from being on at the same time, thereby shunting the high voltage supply to ground.

Abstract: An approximation of entropy is determined on a set of data by comparing subsets of the data. The comparison reveals the regularity and stability of similar patterns amongst subsets of the data. The comparisons perform such that the contribution of noise to measurement of the regularity and stability is minimized. Quantitative values are assigned to measure the degree of regularity and stability. From these quantitative values a single output measure is generated indicative of the amount of patternness of the sequence of data. The calculations required to determine this approximate entropy are preferably performed within a data processing system. Numerous peripheral devices may be attached to such a data processing system. The types of data for which the approximate entropy may be calculated include any sets of data wherein the amount of patternness is sought.

Abstract: An analog computational circuit, for transforming an input voltage into an output voltage or current variable according to a selected transfer function, including a plurality of current sources having a common input and a common current output. Each of the current sources is energizable in response to an input voltage as it exceeds a selected input voltage threshold associated with each of the current sources. There are means coupled to the current sources for establishing the input voltage threshold associated with each of the current sources. Also included are means coupled to each of the current sources for establishing the selected transfer function of the computational circuit. Each of the current sources is adapted to begin conducting current in response to an input voltage which exceeds its associated input voltage threshold, and to provide an attenuated output current proportional to the input voltage, the proporation established by the selected transfer function.

Abstract: A current sensor and limiter provides an output current having a value which is a sum of at least a portion of an input current and a reference current. The current sensor senses an input current which exceeds the reference current, and activates a current shunt which diverts from the input current, an amount of current which is equal to the amount of current by which the input current exceeds the reference current.

Abstract: A power supply reset circuit with a PNP transistor for detecting saturation of an NPN transistor and resetting a fault latch. The PNP and NPN transistors may be separate, discrete components. A preferred embodiment includes a vertical NPN transistor formed in a semiconductor substrate and includes a base, emitter and collector region. The functional, lateral PNP transistor is also fashioned in the semiconductor substrate and has a base region formed by the collector region of the NPN transistor, an emitter region formed by the base region of the NPN transistor, and a distinct, separate collector region disposed in selected proximity to the base and emitter region of the vertical NPN transistor, forming a saturation detector.

Abstract: A high current gain high-frequency planar process PNP transistor comprising an emitter region and a surrounding annular collector. The surface of the transistor is covered with an insulative oxide layer, with an aperture to the emitter region. An overlaying metal layer is provided which substantially covers the base region between the emitter and collector. Connection to the emitter region is provided with an extension of the metal surface to the aperture. However except for this connection, the surface area above the emitter region is not covered by the metal layer. The resulting transistor provides a high-frequency PNP transistor with significantly enhanced Beta.

Abstract: A high speed analog amplifier having a differential input and provides a single output signal which corresponds to the absolute value of the input voltage. Furthermore, the amplifier provides a selectable output offset voltage which is proportional to a selected reference voltage. Moreover, the reference voltage alone is sufficient to operate the amplifier, eliminating additional power supply connections.

Abstract: A threshold comparator having hysteresis wherein the repeatable threshold levels are established by multiple current paths and resistance ratios, which provides an under-voltage lock-out signal. The current paths are established by transistors fabricated on a common substrate and include a split collector P-N-P transistor that provides the distribution of the input signal to the various current paths. The turn-on and turn-off threshold points of the circuit according to the present invention are established by resistance ratios which are more easily maintained than are absolute resistance values. Similarly, when implemented on a common substrate, the remaining component values may be selected so that the thresholds values are nearly independent of temperature, providing an easily manufactured, high yield circuit.

Abstract: A band-gap voltage reference having reduced output voltage noise. The invention embraces several novel concepts, including the optimization of transistor area ratios as used in the band-gap device, the selection of multiple transistors in the Vbe, the section of the current range for the band-gap device, resistive loads to provide minimum load noise and selective signal filtering before the output amplifier. The resulting device according to the present invention exhibits lower output voltage noise than previous band-gap voltage references, without sacrificing other important voltage reference parameters, such as line regulation, load regulation, temperature coefficient, and stability.

Abstract: An improved input ranging divider and method for an analog to digital converter in which a floating common input line to the A to D comparator is coupled through an R/2R resistive input ladder. A constant reference voltage is applied to the other comparator input. By applying an input voltage to a certain input terminal or terminals of the input ranging divider, while the remaining terminals are either grounded or left floating, a wide range of diverse operating ranges may be made available to an A to D converter while utilizing only a small overall number of inputs.

Abstract: A power driver circuit which provides a low voltage drop thereacross when turned on, without being driven into hard saturation. Hard saturation of the circuit according to the present invention is prevented by additional circuit elements which allow the transistor output circuit to be turned on while diverting excess drive current away from the input transistor. As a result, the driver circuit can provide the low saturation voltage and avoid unnecessary saturation of the output transistor while maintaining high-speed switching operation. The circuit may be implemented by discrete components, by a single integrated circuit or part of a larger integrated circuit.

Abstract: A circuit for driving a serial data bus with serial logic data that is supplied to the circuit while buffering the logic data supplying circuit from the data bus. The circuit provides logic output pulses having controlled slew rates wherein the input logic data is not distorted but which inhibits undesired high frequency components associated with the fast rise and fall times of the leading and trailing edges of the input logic data pulses. The circuit comprises an inverting amplifier having capacitive feedback between the output and the inverting input of the amplifier, a buffer amplifier between the output of the inverting amplifier and the output of the circuit, and current switching circuitry for sinking and sourcing currents of equal magnitude at the input of the inverting amplifier depending on the relative magnitude of the input logic data pulses.

Abstract: This relates to a circuit for clamping the voltage across first and second terminals (in this case the gate and source electrodes of a power MOSFET) in response to the receipt of a signal indicating a load fault. An input turnaround transistor receives the signal indicative of the fault and generates a current in response thereto which is applied to the base of a switching transistor. When this current exceeds a predetermined value, the switching transistor turns on which in turn causes a buffer circuit including a PNP transistor to turn on. When the buffer circuit turns on, current is drawn through a zener diode which is coupled to the second terminal. Thus, the clamping circuit between the gate and source terminals equals the voltage drop across the zener diode plus that dropped across the buffer circuit plus the saturation voltage of the switching transistor. Resistors are provided in the buffer circuit to provide for a certain amount of adjustment of the clamping voltage.

Abstract: A two terminal monolithic integrated clamp circuit includes first and second circuits coupled between the two input terminals thereof for clamping the voltage appearing across the two terminals to a predetermined voltage. The first circuit is responsive to the voltage level appearing at the first terminal exceeding the voltage level at the second terminal by said predetermined amount for clamping the voltage level thereat while shunting the majority of the current through the clamping circuit to substrate ground of the integrated circuit. The second circuit is responsive to the voltage level appearing at the second terminal exceeding the voltage level at the first terminal by said predetermined amount for clamping the voltage thereat while shunting the majority of the current to substrate ground.

Abstract: This relates to a comparator circuit for monitoring intelligence on a data bus, which circuit consumes no power until activated by a predetermined voltage on the data bus. An input PNP transistor has a base coupled to the data bus. An emitter resistor and a collector resistor may be scaled to achieve a desired switching threshold. A second PNP transistor has a base coupled to the bus and an emitter coupled to the collector of the first PNP transistor such that the second PNP transistor does not turn on until the first PNP transistor saturates. The collector of the second PNP transistor is coupled to the base of an output NPN transistor and supplies drive thereto when the second PNP transistor is on.

Abstract: This relates to a programmable ring oscillator which comprises a plurality of series coupled gates the output of the last of which is fed back to the input of the first. Bypass means are coupled across the outputs of selected gates so as to in effect increase or decrease the length of the string. In one embodiment, laser trimmable fuses are employed in the bypass networks. In a second embodiment, a data selector under external control is employed.

Abstract: A monolithic integrated temperature compensated voltage reference circuit that includes a thermal source circuit for producing a current at an output thereof having a positive temperature coefficient and an output circuit coupled to the thermal source circuit which is responsive to this current for establishing an output voltage having a substantially zero temperature coefficient associated therewith.