Patents by Inventor Robert A. Rosenberg
Robert A. Rosenberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060012014Abstract: The present invention provides a plastically and/or viscoelastically deformable layer that can be used in conjunction with a low-k dielectric (k of less than 4.0) to provide an electronic semiconductor structure having improved reliability. The deformable layer can be incorporated into various points within an electronic structure to dissipate energy within the structure that may cause the low-k dielectric material to crack or delaminate therefrom. Moreover, the presence of the deformable layer with the electronic structure improves the overall strength of the resultant structure.Type: ApplicationFiled: July 15, 2004Publication date: January 19, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shyng-Tsong Chen, Stefanie Chiras, Michael Lane, Qinghuang Lin, Robert Rosenberg, Thomas Shaw, Terry Spooner
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Publication number: 20060006070Abstract: A conducting material comprising: a conducting core region comprising copper and from 0.001 atomic percent to 0.6 atomic percent of one or more metals selected from iridium, osmium and rhenium; and an interfacial region. The interfacial region comprises at least 80 atomic percent or greater of the one or more metals. The invention is also directed to a method of making a conducting material comprising: providing an underlayer; contacting the underlayer with a seed layer, the seed layer comprising copper and one or more metals selected from iridium, osmium and rhenium; depositing a conducting layer comprising copper on the seed layer, and annealing the conducting layer at a temperature sufficient to cause grain growth in the conducting layer, yet minimize the migration of the one or more alloy metals from the seed layer to the conducting layer.Type: ApplicationFiled: July 9, 2004Publication date: January 12, 2006Applicant: International Business Machines CorporationInventors: Michael Lane, Stefanie Chiras, Terry Spooner, Robert Rosenberg, Daniel Edelstein
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Publication number: 20050266673Abstract: The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing.Type: ApplicationFiled: July 19, 2005Publication date: December 1, 2005Applicant: International Business Machines CorporationInventors: Chao-Kun Hu, Robert Rosenberg, Judith Rubino, Carlos Sambucetti, Anthony Stamper
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Publication number: 20050255562Abstract: The present invention provides methods, processes and reaction mixtures, which produce sulfated heparosan polysaccharides. This invention also provides methods and reaction mixtures for the synthesis of N-deacetylate N-sulfate derivatives of non-sulfated N-acetyl heparosan (HS) polysaccharides.Type: ApplicationFiled: November 12, 2004Publication date: November 17, 2005Inventors: Robert Rosenberg, Kuberan Balagurunathan
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Publication number: 20050127514Abstract: In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.Type: ApplicationFiled: December 8, 2003Publication date: June 16, 2005Inventors: Shyng-Tsong Chen, Stefanie Chiras, Matthew Colburn, Timothy Dalton, Jeffrey Hedrick, Elbert Huang, Kaushik Kumar, Michael Lane, Kelly Malone, Chandrasekhar Narayan, Satyanarayana Nitta, Sampath Purushothaman, Robert Rosenberg, Christy Tyberg, Roy Yu
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Publication number: 20050118796Abstract: An electrically conductive metallic interconnect in a trench or via in a dielectric is provided by depositing a first liner layer on the walls and bottom of the trench or via; removing residual contamination from the bottom of the trench or via; depositing a second liner layer in the trench; depositing a seed layer and filling the trench with electrically conductive metallic material.Type: ApplicationFiled: November 28, 2003Publication date: June 2, 2005Inventors: Stefanie Chiras, Michael Lane, Robert Rosenberg, Terry Spooner
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Publication number: 20050086142Abstract: Methods are provided for lease guaranty services. A landlord enters into an arrangement with a lease guaranty service provider including an agreed upon lease guaranty policy to cover a rental property associated with the landlord. Under the lease guaranty policy, the landlord is a beneficiary and is bound to some contractual duties. A tenant, interested in renting the rental property, enters into a lease guaranty participation agreement with the lease guaranty service provider, which provides that the lease guaranty service provider pays the landlord a claim amount, resulted from the tenant's failure to comply with a lease signed between the tenant and the landlord for the rental property, and the tenant is legally liable to the lease guaranty service provider.Type: ApplicationFiled: October 15, 2003Publication date: April 21, 2005Applicant: RS Reinsurance (Bermuda) Ltd.Inventors: Jeffrey Geller, Robert Rosenberg, Richard O'Connell, Paul Schack
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Patent number: 6831364Abstract: A method for forming a porous dielectric material layer in an electronic structure and the structure formed are disclosed. In the method, a porous dielectric layer in a semiconductor device can be formed by first forming a non-porous dielectric layer, then partially curing, patterning by reactive ion etching, and final curing the non-porous dielectric layer at a higher temperature than the partial curing temperature to transform the non-porous dielectric material into a porous dielectric material, thus forming a dielectric material that has a low dielectric constant, i.e. smaller than 2.6. The non-porous dielectric material may be formed by embedding a thermally stable dielectric material such as methyl silsesquioxane, hydrogen silsesquioxane, benzocyclobutene or aromatic thermoset polymers with a second phase polymeric material therein such that, at the higher curing temperature, the second phase polymeric material substantially volatilizes to leave voids behind forming a void-filled dielectric material.Type: GrantFiled: August 1, 2002Date of Patent: December 14, 2004Assignee: International Business Machines CorporationInventors: Timothy Joseph Dalton, Stephen Edward Greco, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Kenneth Parker Rodbell, Robert Rosenberg
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Patent number: 6812143Abstract: The barrier material of the invention provides for the electrodeposition of copper. The barrier layer includes a dielectric interface surface region, and a copper interface surface region with at least 50 atom percent of a copper interface metal. In particular, the barrier layer of the invention provides for the electrodeposition of copper or copper alloy directly onto the copper interface region of the barrier layer in a direct electrodeposition process. The process includes providing a dielectric layer disposed on an underlayer, contacting a barrier layer to the dielectric layer, and depositing a conducting layer onto the barrier layer.Type: GrantFiled: October 24, 2002Date of Patent: November 2, 2004Assignee: International Business Machines CorporationInventors: Michael Lane, Fenton Read McFeely, Conal Murray, Robert Rosenberg
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Publication number: 20040195694Abstract: An amorphous dielectric material having a dielectric constant of 10 or greater is provided herein for use in fabricating capacitors in integrated circuit applications. The amorphous dielectric material is formed using temperatures below 450° C.; therefore the BEOL metallurgy is not adversely affected. The amorphous dielectric material of the present invention exhibits. good conformality and a low leakage current. Damascene devices containing the capacitor of the present invention are also disclosed.Type: ApplicationFiled: April 23, 2004Publication date: October 7, 2004Applicant: International Business Machines CorporationInventors: Peter Richard Duncombe, Daniel Charles Edelstein, Robert Benjamin Laibowitz, Deborah Ann Neumayer, Tak Hung Ning, Robert Rosenberg, Thomas Mcarraoll Shaw
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Publication number: 20040191870Abstract: Disclosed are methods of 6-O-sulfating glucosaminyl N-acetylglucosamine residues (GlcNAc) in a polysaccharide preparation and methods of converting anticoagulant-inactive heparan sulfate to anticoagulant-active heparan sulfate and substantially pure polysaccharide preparations may by such methods. Also disclosed is a mutant CHO cell which hyper-produces anticoagulant-active heparan sulfate. Methods for elucidating the sequence of activity of enzymes in a biosynthetic pathway are provided.Type: ApplicationFiled: March 25, 2004Publication date: September 30, 2004Inventors: Robert Rosenberg, Lijuan Zhang, David L Beeler
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Patent number: 6787912Abstract: A barrier material that is particularly suited as a barrier layer in copper interconnects structures found in semiconductor structures. The barrier layer contains one or more regions with one region containing at least 50 atom percent of a copper interface metal. The copper interface metal is selected from ruthenium, rhodium, palladium, silver, gold, platinum, iridium, selenium, tellurium, or alloys thereof. The barrier layer also contains a dielectric interface material.Type: GrantFiled: April 26, 2002Date of Patent: September 7, 2004Assignee: International Business Machines CorporationInventors: Michael Lane, Fenton Read McFeely, Conal Murray, Robert Rosenberg
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Patent number: 6777809Abstract: An amorphous dielectric material having a dielectric constant of 10 or greater is provided herein for use in fabricating capacitors in integrated circuit applications. The amorphous dielectric material is formed using temperatures below 450° C.; therefore the BEOL metallurgy is not adversely affected. The amorphous dielectric material of the present invention exhibits good conformality and a low leakage current. Damascene devices containing the capacitor of the present invention are also disclosed.Type: GrantFiled: December 19, 2002Date of Patent: August 17, 2004Assignee: International Business Machines CorporationInventors: Peter Richard Duncombe, Daniel Charles Edelstein, Robert Benjamin Laibowitz, Deborah Ann Neumayer, Tak Hung Ning, Robert Rosenberg, Thomas Mcarraoll Shaw
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Publication number: 20040113277Abstract: In integrated circuit technology; an electromigration and diffusion sensitive conductor of a metal such as copper and processing procedure therefore is provided, wherein, at a planarized chemical mechanical processed interfacing surface, the conductor metal is positioned in a region of a selectable low K eff dielectric material surrounded by a material selected to be protection from outdiffusion and a source of a film thickness cap that is to form over the conductor metal and/or serve as a catalytic layer for electroless selective deposition of a CoWP capping layer.Type: ApplicationFiled: December 11, 2002Publication date: June 17, 2004Inventors: Stefanie Ruth Chiras, Michael Wayne Lane, Sandra Guy Malhotra, Fenton Reed Mc Feely, Robert Rosenberg, Carlos Juan Sambucetti, Philippe Mark Vereecken
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Publication number: 20030203617Abstract: The barrier material of the invention provides for the electrodeposition of copper. The barrier layer includes a dielectric interface surface region, and a copper interface surface region with at least 50 atom percent of a copper interface metal. In particular, the barrier layer of the invention provides for the electrodeposition of copper or copper alloy directly onto the copper interface region of the barrier layer in a direct electrodeposition process. The process includes providing a dielectric layer disposed on an underlayer, contacting a barrier layer to the dielectric layer, and depositing a conducting layer onto the barrier layer.Type: ApplicationFiled: October 24, 2002Publication date: October 30, 2003Inventors: Michael Lane, F. R. McFeely, Conal Murray, Robert Rosenberg
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Publication number: 20030201537Abstract: A barrier material that is particularly suited as a barrier layer in copper interconnects structures found in semiconductor structures. The barrier layer contains one or more regions with one region containing at least 50 atom percent of a copper interface metal. The copper interface metal is selected from ruthenium, rhodium, palladium, silver, gold, platinum, iridium, selenium, tellurium, or alloys thereof. The barrier layer also contains a dielectric interface material.Type: ApplicationFiled: April 26, 2002Publication date: October 30, 2003Applicant: International Business Machines CorporationInventors: Michael Lane, F. R. McFeely, Conal Murray, Robert Rosenberg
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Publication number: 20030089943Abstract: An amorphous dielectric material having a dielectric constant of 10 or greater is provided herein for use in fabricating capacitors in integrated circuit applications. The amorphous dielectric material is formed using temperatures below 450° C.; therefore the BEOL metallurgy is not adversely affected. The amorphous dielectric material of the present invention exhibits good conformality and a low leakage current. Damascene devices containing the capacitor of the present invention are also disclosed.Type: ApplicationFiled: December 19, 2002Publication date: May 15, 2003Applicant: International Business Machines CorporationInventors: Peter Richard Duncombe, Daniel Charles Edelstein, Robert Benjamin Laibowitz, Deborah Ann Neumayer, Tak Hung Ning, Robert Rosenberg, Thomas Mcarraoll Shaw
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Publication number: 20030085447Abstract: An IC including a resistor which is coupled to a metal wiring level through metal contacts, said resistor including a discrete metal-insulator-metal stack, wherein said metal contacts are in contact to one of said metals of said film stack. In the above IC design, current flows laterally through either the top metal electrode, the bottom metal electrode, or both, and any unused electrode is disconnected from the circuit.Type: ApplicationFiled: December 16, 2002Publication date: May 8, 2003Applicant: International Business Machines CorporationInventors: Peter Richard Duncombe, Daniel Charles Edelstein, Robert Benjamin Laibowitz, Deborah Ann Neumayer, Tak Hung Ning, Robert Rosenberg, Thomas McCarroll Shaw
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Publication number: 20030057414Abstract: A method for forming a porous dielectric material layer in an electronic structure and the structure formed are disclosed. In the method, a porous dielectric layer in a semiconductor device can be formed by first forming a non-porous dielectric layer, then partially curing, patterning by reactive ion etching, and final curing the non-porous dielectric layer at a higher temperature than the partial curing temperature to transform the non-porous dielectric material into a porous dielectric material, thus achieving as dielectric material that has significantly improved dielectric constant, i.e. smaller than 2.6.Type: ApplicationFiled: August 1, 2002Publication date: March 27, 2003Applicant: International Business Machines CorporationInventors: Timothy Joseph Dalton, Stephen Edward Greco, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Kenneth Parker Rodbell, Robert Rosenberg
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Patent number: D476726Type: GrantFiled: May 13, 2002Date of Patent: July 1, 2003Inventor: Robert Rosenberg