Patents by Inventor Robert A. Rosenberg
Robert A. Rosenberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6525427Abstract: An amorphous dielectric material having a dielectric constant of 10 or greater is provided herein for use in fabricating capacitors in integrated circuit applications. The amorphous dielectric material is formed using temperatures below 450° C.; therefore the BEOL metallurgy is not adversely affected. The amorphous dielectric material of the present invention exhibits good conformality and a low leakage current. Damascene devices containing the capacitor of the present invention are also disclosed.Type: GrantFiled: January 22, 2002Date of Patent: February 25, 2003Assignee: International Business Machines CorporationInventors: Peter Richard Duncombe, Daniel Charles Edelstein, Robert Benjamin Laibowitz, Deborah Ann Neumayer, Tak Hung Ning, Robert Rosenberg, Thomas Mcarraoll Shaw
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Patent number: 6503641Abstract: An electrical conductor for use in an electronic structure is disclosed which includes a conductor body that is formed of an alloy including between about 0.001 atomic % and about 2 atomic % of an element selected from the group consisting of Ti, Zr, In, Sn and Hf; and a liner abutting the conductor body which is formed of an alloy that includes Ta, W, Ti, Nb and V. The invention further discloses a liner for use in a semiconductor interconnect that is formed of a material selected from the group consisting of Ti, Hf, In, Sn, Zr and alloys thereof, TiCu3, Ta1−XTix, Ta1−X, Hfx, Ta1−X, Inxy, Ta1−XSnx, Ta1−XZrx.Type: GrantFiled: December 18, 2000Date of Patent: January 7, 2003Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Roy Arthur Carruthers, James McKell Edwin Harper, Chao-Kun Hu, Kim Yang Lee, Ismail Cevdet Noyan, Robert Rosenberg, Thomas McCarroll Shaw
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Publication number: 20020175418Abstract: The present invention is directed to an alpha-W layer which is employed in interconnect structures such as trench capacitors or damascene wiring levels as a diffusion barrier layer. The alpha-W layer is a single phased material that is formed by a low temperature/pressure chemical vapor deposition process using tungsten hexacarbonyl, W(CO)6, as the source material.Type: ApplicationFiled: July 3, 2002Publication date: November 28, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephan Alan Cohen, Fenton Read McFeely, Cevdet Ismail Noyan, Kenneth Parker Rodbell, Robert Rosenberg, John Jacob Yurkas
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Patent number: 6452276Abstract: The present invention is directed to an alpha-W layer which is employed in interconnect structures such as trench capacitors or damascene wiring levels as a diffusion barrier layer. The alpha-W layer is a single phased material that is formed by a low temperature/pressure chemical vapor deposition process using tungsten hexacarbonyl, W(CO)6, as the source material.Type: GrantFiled: April 30, 1998Date of Patent: September 17, 2002Assignee: International Business Machines CorporationInventors: Stephan A. Cohen, Fenton R. McFeely, Cevdet I. Noyan, Kenneth P. Rodbell, John J. Yurkas, Robert Rosenberg
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Patent number: 6451712Abstract: A method for forming a porous dielectric material layer in an electronic structure and the structure formed are disclosed. In the method, a porous dielectric layer in a semiconductor device can be formed by first forming a non-porous dielectric layer, then partially curing, patterning by reactive ion etching, and final curing the non-porous dielectric layer at a higher temperature than the partial curing temperature to transform the non-porous dielectric material into a porous dielectric material, thus achieving a dielectric material that has significantly improved dielectric constant, i.e. smaller than 2.6.Type: GrantFiled: December 18, 2000Date of Patent: September 17, 2002Assignee: International Business Machines CorporationInventors: Timothy Joseph Dalton, Stephen Edward Greco, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Kenneth Parker Rodbell, Robert Rosenberg
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Publication number: 20020098681Abstract: The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing.Type: ApplicationFiled: November 13, 2001Publication date: July 25, 2002Inventors: Chao-Kun Hu, Robert Rosenberg, Judith Marie Rubino, Carlos Juan Sambucetti, Anthony Kendall Stamper
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Patent number: 6417572Abstract: A process for producing a multi-level semiconductor device having metal interconnections with insulating passivation layers and the product produced thereby. The product and process improve the resistance of the metallization interconnections to extrusion-short electromigration failures by preventing the insulating passivation layers from cracking. The product and process also reduce the level of resistance saturation or the maximum resistance shift caused by electromigration. By replacing wide-line metallization interconnection conducting lines surrounded by insulating passivation layers with two or more narrow, parallel conducting lines having aspect ratios less than or equal to unity with passivation layers located in between, the incidence of passivation cracking and extrusion-short failures is reduced.Type: GrantFiled: July 16, 1999Date of Patent: July 9, 2002Assignee: International Business Machines CorporationInventors: Dureseti Chidambarrao, Ronald G. Filippi, Robert Rosenberg, Thomas M. Shaw, Timothy D. Sullivan, Richard A. Wachnik
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Publication number: 20020074659Abstract: A method for forming a porous dielectric material layer in an electronic structure and the structure formed are disclosed. In the method, a porous dielectric layer in a semiconductor device can be formed by first forming a non-porous dielectric layer, then partially curing, patterning by reactive ion etching, and final curing the non-porous dielectric layer at a higher temperature than the partial curing temperature to transform the non-porous dielectric material into a porous dielectric material, thus achieving a dielectric material that has significantly improved dielectric constant, i.e. smaller than 2.6.Type: ApplicationFiled: December 18, 2000Publication date: June 20, 2002Applicant: International Business Machines CorporationInventors: Timothy Joseph Dalton, Stephen Edward Greco, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Kenneth Parker Rodbell, Robert Rosenberg
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Publication number: 20020076574Abstract: An electrical conductor for use in an electronic structure is disclosed which includes a conductor body that is formed of an alloy including between about 0.001 atomic % and about 2 atomic % of an element selected from the group consisting of Ti, Zr, In, Sn and Hf; and a liner abutting the conductor body which is formed of an alloy that includes Ta, W, Ti, Nb and V. The invention further discloses a liner for use in a semiconductor interconnect that is formed of a material selected from the group consisting of Ti, Hf, In, Sn, Zr and alloys thereof, TiCu3, Ta1−XTix, Ta1−XHfx, Ta1−XInxy, Ta1−XSnx, Ta1−XZrx.Type: ApplicationFiled: December 18, 2000Publication date: June 20, 2002Applicant: International Business Machines CorporationInventors: Cyril Cabral, Roy Arthur Carruthers, James McKell Edwin Harper, Chao-Kun Hu, Kim Yang Lee, Ismail Cevdet Noyan, Robert Rosenberg, Thomas McCarroll Shaw
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Publication number: 20020066919Abstract: An amorphous dielectric material having a dielectric constant of 10 or greater is provided herein for use in fabricating capacitors in integrated circuit applications. The amorphous dielectric material is formed using temperatures below 450° C.; therefore the BEOL metallurgy is not adversely affected. The amorphous dielectric material of the present invention exhibits good conformality and a low leakage current. Damascene devices containing the capacitor of the present invention are also disclosed.Type: ApplicationFiled: January 22, 2002Publication date: June 6, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peter Richard Duncombe, Daniel Charles Edelstein, Robert Benjamin Laibowitz, Deborah Ann Neumayer, Tak Hung Ning, Robert Rosenberg, Thomas McCarraoll Shaw
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Patent number: 6342733Abstract: The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing.Type: GrantFiled: July 27, 1999Date of Patent: January 29, 2002Assignee: International Business Machines CorporationInventors: Chao-Kun Hu, Robert Rosenberg, Judith Marie Rubino, Carlos Juan Sambucetti, Anthony Kendall Stamper
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Publication number: 20010040271Abstract: An IC including a resistor which is coupled to a metal wiring level through metal contacts, said resistor including a discrete metal-insulator-metal stack, wherein said metal contacts are in contact to one of said metals of said film stack. In the above IC design, current flows laterally through either the top metal electrode, the bottom metal electrode, or both, and any unused electrode is disconnected from the circuit.Type: ApplicationFiled: January 9, 2001Publication date: November 15, 2001Inventors: Peter Richard Duncombe, Daniel Charles Edelstein, Robert Benjamin Laibowitz, Deborah Ann Neumayer, Tak Hung Ning, Robert Rosenberg, Thomas McCarroll Shaw
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Publication number: 20010013660Abstract: An amorphous dielectric material having a dielectric constant of 10 or greater is provided herein for use in fabricating capacitors in integrated circuit applications. The amorphous dielectric material is formed using temperatures below 450° C.; therefore the BEOL metallurgy is not adversely affected. The amorphous dielectric material of the present invention exhibits good conformality and a low leakage current. Damascene devices containing the capacitor of the present invention are also disclosed.Type: ApplicationFiled: January 4, 1999Publication date: August 16, 2001Inventors: PETER RICHARD DUNCOMBE, DANIEL CHARLES EDELSTEIN, ROBERT BENJAMIN LAIBOWITZ, DEBORAH ANN NEUMAYER, TAK HUNG NING, ROBERT ROSENBERG, THOMAS MCARRAOLL SHAW
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Patent number: 6264885Abstract: A metal/ferrite laminate magnet has perforations forming apertures in the magnet. The magnet is formed of outside metal plates surrounding a sandwich of two layers of ferrite material. The outside metal plates allow the perforations to be made in the magnet before sintering of the magnet and maintain the alignment of the holes during sintering. The metal plates also provide the magnet with mechanical robustness and rigidity and prevent cracking occurring between adjacent apertures.Type: GrantFiled: August 18, 1999Date of Patent: July 24, 2001Assignee: International Business Machines CorporationInventors: John Ulrich Knickerbocker, Andrew Ramsay Knox, Robert Rosenberg
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Patent number: 5986395Abstract: A metal/ferrite laminate magnet has perforations forming apertures in the magnet. The magnet is formed of outside metal plates surrounding a sandwich of two layers of ferrite material. The outside metal plates allow the perforations to be made in the magnet before sintering of the magnet and maintain the alignment of the holes during sintering. The metal plates also provide the magnet with mechanical robustness and rigidity and prevent cracking occurring between adjacent apertures.Type: GrantFiled: May 9, 1997Date of Patent: November 16, 1999Assignee: International Business Machines CorporationInventors: John Ulrich Knickerbocker, Andrew Ramsay Knox, Robert Rosenberg
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Patent number: 5857883Abstract: The present invention relates generally to a new metal/ferrite laminate magnet and process thereof. More particularly, the invention encompasses a new process for fabrication of a large area laminate magnet with a significant number of perforated holes, integrated metal plate(s) and electrodes for electron and electron beam control. The present invention also relates to a magnetic matrix and electron beam source and methods of manufacture thereof.Type: GrantFiled: May 9, 1997Date of Patent: January 12, 1999Assignee: International Business Machines CorporationInventors: John U. Knickerbocker, James N. Humenik, Andrew R. Knox, Robert Rosenberg
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Patent number: 5540785Abstract: A method for fabricating silicon on insulator structures having a dislocation free silicon layer. The method utilizes low temperature UHVCVD to deposit a very heavily doped etch stop layer having a very steep doping profile onto a substrate and a lightly doped active layer onto the etch stop layer. An insulator is formed on the active layer and a carrier wafer is formed on the insulator layer. The original substrate is removed in a first etch and the etch stop layer is removed in a second etch resulting in a thin, uniform active layer. In one embodiment, a small percentage of germanium is added to the etch stop layer to produce a defect free epitaxial active layer.Type: GrantFiled: April 4, 1994Date of Patent: July 30, 1996Assignee: International Business Machines CorporationInventors: Robert H. Dennard, Bernard S. Meyerson, Robert Rosenberg
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Patent number: 5462883Abstract: A method for fabricating silicon on insulator structures having a dislocation free silicon layer. The method utilizes low temperature UHVCVD to deposit a very heavily doped etch stop layer having a very steep doping profile onto a substrate and a lightly doped active layer onto the etch stop layer. An insulator is formed on the active layer and a carrier wafer is formed on the insulator layer. The original substrate is removed in a first etch and the etch stop layer is removed in a second etch resulting in a thin, uniform active layer. In one embodiment, a small percentage of germanium is added to the etch stop layer to produce a defect free epitaxial active layer.Type: GrantFiled: April 11, 1994Date of Patent: October 31, 1995Assignee: International Business Machines CorporationInventors: Robert H. Dennard, Bernard S. Meyerson, Robert Rosenberg
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Patent number: 5254318Abstract: A reformer tube assembly for use in reformer reactors including a ceramic tube having an open top end and a closed bottom end, a corrosive resistant liner for the ceramic tube also having an open top end and closed bottom end and a centrally disposed metal tube having an open top end and open bottom end wherein the centrally disposed metal tube has a diameter substantially less than the liner so as to form an annulus between the interior of the liner and the exterior of the centrally disposed tube in which catalyst for the reaction is placed, and the open bottom end of the centrally disposed tube is spaced away from the closed bottom of the liner to allow process gas exiting the catalyst filled annulus to pass along the closed bottom of the liner and up the interior of the centrally disposed metal tube.Type: GrantFiled: July 20, 1992Date of Patent: October 19, 1993Assignee: Stone & Webster Engineering CorporationInventors: Joseph J. Williams, Robert A. Rosenberg, Lane J. McDonough
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Patent number: 5132765Abstract: There is provided a method for use in the fabrication of a transistor, the method including the steps of: providing a substrate of semiconductor material including a region of first conductivity type; forming a first layer of second conductivity type epitaxial semiconductor material over the region; forming a second layer of second conductivity type epitaxial semiconductor material over the first layer, the second layer of a relatively higher dopant concentration than the first layer; oxidizing a portion of the second layer; and removing the oxidized portion of the second layer to expose a portion of the first layer, the exposed portion of the first layer forming an intrinsic base region. The steps of forming the first and second layers are preferably performed using low temperature, ultra-high vacuum, epitaxial deposition processes.Type: GrantFiled: January 31, 1991Date of Patent: July 21, 1992Inventors: Jeffrey L. Blouse, Inge G. Fulton, Russell C. Lange, Bernard S. Meyerson, Karen A. Nummy, Martin Revitz, Robert Rosenberg