Patents by Inventor Robert Aigner

Robert Aigner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11025224
    Abstract: RF circuitry, which includes a first acoustic RF resonator (ARFR) and a first compensating ARFR, is disclosed. A first inductive element is coupled between the first compensating ARFR and a first end of the first ARFR. A second inductive element is coupled between the first compensating ARFR and a second end of the first ARFR. The first compensating ARFR, the first inductive element, and the second inductive element at least partially compensate for a parallel capacitance of the first ARFR.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: June 1, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Nadim Khlat, Jean-Frederic Chiron, Marcus Granger-Jones, Andrew F. Folkmann, Robert Aigner
  • Patent number: 11011498
    Abstract: The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: May 18, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner, Gernot Fattinger, Dirk Robert Walter Leipold, George Maxim, Baker Scott, Merrill Albert Hatcher, Jr., Jon Chadwick
  • Patent number: 11005450
    Abstract: A filter circuit includes a first input node and a second input node for receiving an input signal, and a first output node and a second output node for providing an output signal. A first series acoustic resonator is coupled in series between the first input node and the first output node. At least one coupled resonator filter (CRF) includes first and second transducers, which may be acoustically coupled to one another. The first transducer has a first electrode coupled to the first input node, a second electrode coupled to the second input node, and a first piezoelectric layer between the first electrode and the second electrode. A second transducer has a third electrode coupled to the first output node, a fourth electrode coupled to the second output node, and a second piezoelectric layer between the third electrode and the fourth electrode.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: May 11, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Nadim Khlat, Robert Aigner
  • Patent number: 10964672
    Abstract: The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: March 30, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner, Gernot Fattinger, Dirk Robert Walter Leipold, George Maxim, Baker Scott, Merrill Albert Hatcher, Jr., Jon Chadwick
  • Patent number: 10958245
    Abstract: A filter circuit includes a first input node and a second input node for receiving an input signal, and a first output node and a second output node for providing an output signal. A first series acoustic resonator is coupled in series between the first input node and the first output node. At least one coupled resonator filter (CRF) includes first and second transducers, which may be acoustically coupled to one another. The first transducer has a first electrode coupled to the first input node, a second electrode coupled to the second input node, and a first piezoelectric layer between the first electrode and the second electrode. A second transducer has a third electrode coupled to the first output node, a fourth electrode coupled to the second output node, and a second piezoelectric layer between the third electrode and the fourth electrode.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: March 23, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Nadim Khlat, Robert Aigner
  • Patent number: 10873318
    Abstract: Filter circuits having acoustic wave resonators in a transversal configuration are disclosed. In the transversal configuration, the acoustic wave resonators are arranged transverse to an input and output port of the filter circuit. As such, all the acoustic wave resonators of the filter circuit are connected to the input port and connected to the output port. In the transversal configuration, the filter circuit can be designed for any transfer function without being restricted to a coupling coefficient of a piezoelectric material used in the acoustic wave resonators. In this regard, the filter circuit can achieve very wideband filter responses, multiband responses, and/or responses with arbitrary position of transmission zeros. The filter circuit having the transversal configuration can also be designed for complex transmission zeros for phase equalization.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: December 22, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Jordi Mateu, Carlos Collado Gomez, Alberto Hueltes Escobar, Robert Aigner, Nadim Khlat
  • Patent number: 10804246
    Abstract: The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: October 13, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner, Gernot Fattinger, Dirk Robert Walter Leipold, George Maxim, Baker Scott, Merrill Albert Hatcher, Jr., Jon Chadwick
  • Publication number: 20200317507
    Abstract: A wire-based microelectromechanical systems (MEMS) apparatus is provided. In examples discussed herein, the wire-based MEMS apparatus includes a MEMS control bus and at least one passive MEMS switch circuit. The passive MEMS switch circuit is configured to close a MEMS switch(es) by generating a constant voltage(s) that exceeds a defined threshold voltage (e.g., 30-50 V). In a non-limiting example, the passive MEMS switch circuit can generate the constant voltage(s) based on a radio frequency (RF) voltage(s), which may be harvested from an RF signal(s) received via the MEMS control bus. In this regard, it may be possible to eliminate active components and/or circuits from the passive MEMS switch circuit, thus helping to reduce leakage and power consumption. As a result, it may be possible to provide the passive MEMS switch circuit in a low power apparatus for supporting such applications as the Internet-of-Things (IoT).
    Type: Application
    Filed: December 19, 2019
    Publication date: October 8, 2020
    Inventors: Nadim Khlat, Robert Aigner
  • Patent number: 10790216
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: September 29, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner
  • Publication number: 20200228089
    Abstract: Bulk acoustic wave (BAW) resonators, and particularly top electrodes with step arrangements for BAW resonators are disclosed. Top electrodes on piezoelectric layers are disclosed that include a border (BO) region with a dual-step arrangement where an inner step and an outer step are formed with increasing heights toward peripheral edges of the top electrode. Dielectric spacer layers may be provided between the outer steps and the piezoelectric layer. Passivation layers are disclosed that extend over the top electrode either to peripheral edges of the piezoelectric layer or that are inset from peripheral edges of the piezoelectric layer. Piezoelectric layers may be arranged with reduced thickness portions in areas that are uncovered by top electrodes. BAW resonators as disclosed herein are provided with high quality factors and suppression of spurious modes while also providing weakened BO modes that are shifted farther away from passbands of such BAW resonators.
    Type: Application
    Filed: July 30, 2019
    Publication date: July 16, 2020
    Inventors: Alireza Tajic, Paul Stokes, Robert Aigner
  • Patent number: 10622967
    Abstract: A filter circuit includes a first input node and a second input node for receiving an input signal, and a first output node and a second output node for providing an output signal. A first series acoustic resonator is coupled in series between the first input node and the first output node. At least one coupled resonator filter (CRF) includes first and second transducers, which may be acoustically coupled to one another. The first transducer has a first electrode coupled to the first input node, a second electrode coupled to the second input node, and a first piezoelectric layer between the first electrode and the second electrode. A second transducer has a third electrode coupled to the first output node, a fourth electrode coupled to the second output node, and a second piezoelectric layer between the third electrode and the fourth electrode.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: April 14, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Nadim Khlat, Robert Aigner
  • Patent number: 10615147
    Abstract: The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: April 7, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner, Gernot Fattinger, Dirk Robert Walter Leipold, George Maxim, Baker Scott, Merrill Albert Hatcher, Jr., Jon Chadwick
  • Patent number: 10600723
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: March 24, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner
  • Patent number: 10574203
    Abstract: A bonded wafer with low carrier lifetime in silicon comprises a silicon substrate having opposing top and bottom surfaces; a piezoelectric layer bonded over the top surface of the silicon substrate and having opposing top and bottom surfaces separated by a distance T; and a pair of electrodes having fingers that are inter-digitally dispersed on the top surface of the piezoelectric layer in a pattern having a center-to-center distance D between adjacent fingers of the same electrode, the electrodes comprising a portion of a Surface Acoustic Wave (SAW) device. A structure of the silicon in a top portion of the silicon substrate has been modified to reduce carrier lifetime and prevent the creation of a parasitic conductance within the top portion of the silicon substrate during operation of the SAW device.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: February 25, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Shogo Inoue, Marc Solal, Robert Aigner
  • Patent number: 10553521
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: February 4, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner
  • Patent number: 10553564
    Abstract: The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: February 4, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner, Gernot Fattinger, Dirk Robert Walter Leipold, George Maxim, Baker Scott, Merrill Albert Hatcher, Jr., Jon Chadwick
  • Patent number: 10547283
    Abstract: Bulk Acoustic Wave (BAW) resonators with a Border (BO) ring and an inner ring are provided. One BAW resonator includes a bottom electrode, a piezoelectric layer over the bottom electrode, and a top electrode over the piezoelectric layer in which an active region is formed where the top electrode and the bottom electrode overlap. The top electrode includes a BO ring extending about a periphery of the active region and an inner ring inside of and spaced apart from the BO ring. The BO ring is a mass loading of a first portion of the top electrode and the inner ring is a mass unloading of a second portion of the top electrode. Various methods include fabricating a BAW resonator with a top electrode including a mass loading BO ring and a mass unloading inner ring spaced apart from the mass loading BO ring.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: January 28, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Alireza Tajic, Paul Stokes, Robert Aigner
  • Publication number: 20190378819
    Abstract: The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.
    Type: Application
    Filed: June 11, 2018
    Publication date: December 12, 2019
    Inventors: Julio C. Costa, Robert Aigner, Gernot Fattinger, Dirk Robert Walter Leipold, George Maxim, Baker Scott, Merrill Albert Hatcher, JR., Jon Chadwick
  • Publication number: 20190378821
    Abstract: The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.
    Type: Application
    Filed: July 31, 2019
    Publication date: December 12, 2019
    Inventors: Julio C. Costa, Robert Aigner, Gernot Fattinger, Dirk Robert Walter Leipold, George Maxim, Baker Scott, Merrill Albert Hatcher, JR., Jon Chadwick
  • Patent number: 10504818
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: December 10, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner