Patents by Inventor Robert Coffie
Robert Coffie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136431Abstract: A high electron mobility transistor (HEMT) device including a substrate, an AlGaN buffer layer on the substrate, where the buffer layer has a percentage of Al between 1% and 6%, an InGaN layer on the buffer layer, where the InGaN layer has about 10% of In, a GaN channel layer on the InGaN layer, and an AlGaN barrier layer on the channel layer. In one embodiment, the buffer layer is Al0.04Ga0.96N, the InGaN layer is about 2 nm thick, and the barrier layer is Al0.34Ga0.66N. The HEMT device may include a nucleation layer between the substrate and the buffer layer, a GaN spacer layer between the buffer layer and the InGaN layer, and/or an AlN interlayer between the channel layer and the barrier layer.Type: ApplicationFiled: October 23, 2022Publication date: April 25, 2024Inventor: Robert Coffie
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Patent number: 9941399Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.Type: GrantFiled: August 19, 2016Date of Patent: April 10, 2018Assignee: Transphorm Inc.Inventors: Umesh Mishra, Robert Coffie, Likun Shen, Ilan Ben-Yaacov, Primit Parikh
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Patent number: 9831315Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.Type: GrantFiled: June 14, 2016Date of Patent: November 28, 2017Assignee: Transphorm Inc.Inventors: Rongming Chu, Robert Coffie
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Publication number: 20160359030Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.Type: ApplicationFiled: August 19, 2016Publication date: December 8, 2016Inventors: Umesh Mishra, Robert Coffie, Likun Shen, Ilan Ben-Yaacov, Primit Parikh
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Publication number: 20160293747Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.Type: ApplicationFiled: June 14, 2016Publication date: October 6, 2016Inventors: Rongming Chu, Robert Coffie
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Patent number: 9437708Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.Type: GrantFiled: November 18, 2015Date of Patent: September 6, 2016Assignee: Transphorm Inc.Inventors: Umesh Mishra, Robert Coffie, Likun Shen, Ilan Ben-Yaacov, Primit Parikh
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Patent number: 9373699Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.Type: GrantFiled: March 17, 2015Date of Patent: June 21, 2016Assignee: Transphorm Inc.Inventors: Rongming Chu, Robert Coffie
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Patent number: 9293458Abstract: An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor both encased in a single package. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, a drain electrode of the high-voltage depletion-mode transistor is electrically connected to a drain lead of the single package, a gate electrode of the low-voltage enhancement-mode transistor is electrically connected to a gate lead of the single package, a gate electrode of the high-voltage depletion-mode transistor is electrically connected to an additional lead of the single package, and a source electrode of the low-voltage enhancement-mode transistor is electrically connected to a conductive structural portion of the single package.Type: GrantFiled: October 18, 2013Date of Patent: March 22, 2016Assignee: Transphorm Inc.Inventors: Primit Parikh, James Honea, Carl C. Blake, Jr., Robert Coffie, Yifeng Wu, Umesh Mishra
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Publication number: 20160071951Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.Type: ApplicationFiled: November 18, 2015Publication date: March 10, 2016Inventors: Umesh Mishra, Robert Coffie, Likun Shen, Ilan Ben-Yaacov, Primit Parikh
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Patent number: 9196716Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.Type: GrantFiled: August 20, 2014Date of Patent: November 24, 2015Assignee: Transphorm Inc.Inventors: Umesh Mishra, Robert Coffie, Likun Shen, Ilan Ben-Yaacov, Primit Parikh
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Patent number: 9171836Abstract: An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.Type: GrantFiled: September 5, 2014Date of Patent: October 27, 2015Assignee: Transphorm Inc.Inventors: Rakesh K. Lal, Robert Coffie, Yifeng Wu, Primit Parikh, Yuvaraj Dora, Umesh Mishra, Srabanti Chowdhury, Nicholas Fichtenbaum
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Patent number: 9111961Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.Type: GrantFiled: February 12, 2014Date of Patent: August 18, 2015Assignee: Transphorm Inc.Inventors: Rongming Chu, Robert Coffie
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Publication number: 20150187893Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.Type: ApplicationFiled: March 17, 2015Publication date: July 2, 2015Inventors: Rongming Chu, Robert Coffie
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Patent number: 9012288Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.Type: GrantFiled: February 12, 2014Date of Patent: April 21, 2015Assignee: Transphorm Inc.Inventors: Rongming Chu, Robert Coffie
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Publication number: 20140377930Abstract: An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.Type: ApplicationFiled: September 5, 2014Publication date: December 25, 2014Inventors: Rakesh K. Lal, Robert Coffie, Yifeng Wu, Primit Parikh, Yuvaraj Dora, Umesh Mishra, Srabanti Chowdhury, Nicholas Fichtenbaum
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Publication number: 20140361309Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.Type: ApplicationFiled: August 20, 2014Publication date: December 11, 2014Inventors: Umesh Mishra, Robert Coffie, Likun Shen, Ilan Ben-Yaacov, Primit Parikh
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Patent number: 8860495Abstract: An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.Type: GrantFiled: October 31, 2013Date of Patent: October 14, 2014Assignee: Transphorm Inc.Inventors: Rakesh K. Lal, Robert Coffie, Yifeng Wu, Primit Parikh, Yuvaraj Dora, Umesh Mishra, Srabanti Chowdhury, Nicholas Fichtenbaum
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Patent number: 8841702Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.Type: GrantFiled: July 30, 2013Date of Patent: September 23, 2014Assignee: Transphorm Inc.Inventors: Umesh Mishra, Robert Coffie, Likun Shen, Ilan Ben-Yaacov, Primit Parikh
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Publication number: 20140162421Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.Type: ApplicationFiled: February 12, 2014Publication date: June 12, 2014Applicant: Transphorm Inc.Inventors: Rongming Chu, Robert Coffie
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Patent number: 8692294Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.Type: GrantFiled: January 24, 2013Date of Patent: April 8, 2014Assignee: Transphorm Inc.Inventors: Rongming Chu, Robert Coffie