Patents by Inventor Robert Coffie
Robert Coffie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140094010Abstract: An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.Type: ApplicationFiled: October 31, 2013Publication date: April 3, 2014Applicant: Transphorm Inc.Inventors: Rakesh L. Lal, Robert Coffie, Yifeng Wu, Primit Parikh, Yuvaraj Dora, Umesh Mishra, Srabanti Chowdhury, Nicholas Fichtenbaum
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Publication number: 20140042495Abstract: An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor both encased in a single package. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, a drain electrode of the high-voltage depletion-mode transistor is electrically connected to a drain lead of the single package, a gate electrode of the low-voltage enhancement-mode transistor is electrically connected to a gate lead of the single package, a gate electrode of the high-voltage depletion-mode transistor is electrically connected to an additional lead of the single package, and a source electrode of the low-voltage enhancement-mode transistor is electrically connected to a conductive structural portion of the single package.Type: ApplicationFiled: October 18, 2013Publication date: February 13, 2014Applicant: Transphorm Inc.Inventors: Primit Parikh, James Honea, Carl C. Blake, Jr., Robert Coffie, Yifeng Wu, Umesh Mishra
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Patent number: 8624662Abstract: An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor both encased in a single package. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, a drain electrode of the high-voltage depletion-mode transistor is electrically connected to a drain lead of the single package, a gate electrode of the low-voltage enhancement-mode transistor is electrically connected to a gate lead of the single package, a gate electrode of the high-voltage depletion-mode transistor is electrically connected to an additional lead of the single package, and a source electrode of the low-voltage enhancement-mode transistor is electrically connected to a conductive structural portion of the single package.Type: GrantFiled: February 5, 2010Date of Patent: January 7, 2014Assignee: Transphorm Inc.Inventors: Primit Parikh, James Honea, Carl C. Blake, Jr., Robert Coffie, Yifeng Wu, Umesh Mishra
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Patent number: 8598937Abstract: An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.Type: GrantFiled: October 7, 2011Date of Patent: December 3, 2013Assignee: Transphorm Inc.Inventors: Rakesh K. Lal, Robert Coffie, Yifeng Wu, Primit Parikh, Yuvaraj Dora, Umesh Mishra, Srabanti Chowdhury, Nicholas Fichtenbaum
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Publication number: 20130316502Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.Type: ApplicationFiled: July 30, 2013Publication date: November 28, 2013Applicant: Transphorm Inc.Inventors: Umesh Mishra, Robert Coffie, Likun Shen, Ilan Ben-Yaacov, Primit Parikh
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Patent number: 8519438Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.Type: GrantFiled: April 23, 2008Date of Patent: August 27, 2013Assignee: Transphorm Inc.Inventors: Umesh Mishra, Robert Coffie, Likun Shen, Ilan Ben-Yaacov, Primit Parikh
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Patent number: 8431962Abstract: A nitride-based FET device that provides reduced electron trapping and gate current leakage. The device includes a relatively thick passivation layer to reduce traps caused by device processing and a thin passivation layer below the gate terminal to reduce gate current leakage. The device includes semiconductor device layers deposited on a substrate. A plurality of passivation layers are deposited on the semiconductor device layers, where at least two of the layers are made of a different dielectric material to provide an etch stop. One or more of the passivation layers can be removed using the interfaces between the layers as an etch stop so that the distance between the gate terminal and the semiconductor device layers can be tightly controlled, where the distance can be made very thin to increase device performance and reduce gate current leakage.Type: GrantFiled: December 7, 2007Date of Patent: April 30, 2013Assignee: Northrop Grumman Systems CorporationInventors: Benjamin Heying, Ioulia Smorchkova, Vincent Gambin, Robert Coffie
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Publication number: 20130088280Abstract: An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.Type: ApplicationFiled: October 7, 2011Publication date: April 11, 2013Applicant: TRANSPHORM INC.Inventors: Rakesh K. Lal, Robert Coffie, Yifeng Wu, Primit Parikh, Yuvaraj Dora, Umesh Mishra, Srabanti Chowdhury, Nicholas Fichtenbaum
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Patent number: 8390000Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.Type: GrantFiled: August 28, 2009Date of Patent: March 5, 2013Assignee: Transphorm Inc.Inventors: Rongming Chu, Robert Coffie
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Publication number: 20110193619Abstract: An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor both encased in a single package. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, a drain electrode of the high-voltage depletion-mode transistor is electrically connected to a drain lead of the single package, a gate electrode of the low-voltage enhancement-mode transistor is electrically connected to a gate lead of the single package, a gate electrode of the high-voltage depletion-mode transistor is electrically connected to an additional lead of the single package, and a source electrode of the low-voltage enhancement-mode transistor is electrically connected to a conductive structural portion of the single package.Type: ApplicationFiled: February 5, 2010Publication date: August 11, 2011Applicant: Transphorm Inc.Inventors: Primit Parikh, James Honea, Carl C. Blake, JR., Robert Coffie, Yifeng Wu, Umesh Mishra
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Publication number: 20110049526Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.Type: ApplicationFiled: August 28, 2009Publication date: March 3, 2011Applicant: TRANSPHORM INC.Inventors: Rongming Chu, Robert Coffie
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Patent number: 7897446Abstract: A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source ohmic vias between the source contact and the protective dielectric layer and between the protective dielectric layer and the drain contact; and a metal T-gate disposed above the barrier layer including a field mitigating plate disposed on a side portion of a stem of the metal T-gate.Type: GrantFiled: March 25, 2010Date of Patent: March 1, 2011Assignee: Northrop Grumman Systems CorporationInventors: Ioulia Smorchkova, Robert Coffie, Ben Heying, Carol Namba, Po-Hsin Liu, Boris Hikin
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Patent number: 7851825Abstract: Enhancement-mode III-nitride transistors are described that have a large source to drain barrier in the off state, low off state leakage, and low channel resistance in the access regions are described. The devices can include a charge depleting layer under the gate and/or a charge enhancing layer outside of the gate region, that is, in the access region.Type: GrantFiled: November 26, 2008Date of Patent: December 14, 2010Assignee: Transphorm Inc.Inventors: Chang Soo Suh, Ilan Ben-Yaacov, Robert Coffie, Umesh Mishra
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Patent number: 7800132Abstract: A semiconductor device includes a T-gate disposed between drain and source regions and above a barrier layer to form a Schottky contact to the channel layer. A first inactive field mitigating plate is disposed above a portion of the T-gate and a second active field plate is disposed above the barrier layer and in a vicinity of the T-gate.Type: GrantFiled: October 25, 2007Date of Patent: September 21, 2010Assignee: Northrop Grumman Systems CorporationInventors: Ioulia Smorchkova, Carol Namba, Po-Hsin Liu, Robert Coffie, Roger Tsai
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Publication number: 20100184262Abstract: A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source ohmic vias between the source contact and the protective dielectric layer and between the protective dielectric layer and the drain contact; and a metal T-gate disposed above the barrier layer including a field mitigating plate disposed on a side portion of a stem of the metal T-gate.Type: ApplicationFiled: March 25, 2010Publication date: July 22, 2010Applicant: Northrop Grumman Space and Mission Systems Corp.Inventors: Ioulia Smorchkova, Robert Coffie, Ben Heying, Carol Namba, Po-Hsin Liu, Boris Hikin
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Patent number: 7750370Abstract: A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source ohmic vias between the source contact and the protective dielectric layer and between the protective dielectric layer and the drain contact; and a metal T-gate disposed above the barrier layer including a field mitigating plate disposed on a side portion of a stem of the metal T-gate.Type: GrantFiled: December 20, 2007Date of Patent: July 6, 2010Assignee: Northrop Grumman Space & Mission Systems Corp.Inventors: Ioulia Smorchkova, Robert Coffie, Ben Heying, Carol Namba, Po-Hsin Liu, Boris Hikin
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Patent number: 7632726Abstract: A method for fabricating a nitride-based FET device that provides reduced electron trapping and gate current leakage. The fabrication method provides a device that includes a relatively thick passivation layer to reduce traps caused by device processing and a thin passivation layer below the gate terminal to reduce gate current leakage. Semiconductor device layers are deposited on a substrate. A plurality of passivation layers are deposited on the semiconductor device layers, where at least two of the layers are made of a different dielectric material to provide an etch stop. One or more of the passivation layers can be removed using the interfaces between the layers as an etch stop so that the distance between the gate terminal and the semiconductor device layers can be tightly controlled, where the distance can be made very thin to increase device performance and reduce gate current leakage.Type: GrantFiled: December 7, 2007Date of Patent: December 15, 2009Assignee: Northrop Grumman Space & Mission Systems Corp.Inventors: Benjamin Heying, Ioulia Smorchkova, Vincent Gambin, Robert Coffie
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Publication number: 20090267078Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.Type: ApplicationFiled: April 23, 2008Publication date: October 29, 2009Applicant: Transphorm Inc.Inventors: Umesh Mishra, Robert Coffie, Likun Shen, Ilan Ben-Yaacov, Primit Parikh
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Publication number: 20090267115Abstract: A method of fabricating a T-gate HEMT with a club extension comprising the steps of: providing a substrate; providing a bi-layer resist on the substrate; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to a T-gate opening; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to the shape of the club extension wherein the area corresponding to the club extension is approximately 1 micron to an ohmic source side of a T-gate and approximately 0.5 microns forward from a front of the T-gate; developing out the bi-layer resist in the exposed area that corresponds to the T-gate opening; developing out the bi-layer resist in the exposed area that corresponds to the club extension; and forming the T-gate and club extension through a metallization process.Type: ApplicationFiled: April 28, 2008Publication date: October 29, 2009Inventors: Carol Osaka Namba, Po-Hsin Liu, Ioulia Smorchkova, Michael Wojtowicz, Robert Coffie, Yaochung Chen
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Patent number: 7608865Abstract: A method of fabricating a T-gate HEMT with a club extension comprising the steps of: providing a substrate; providing a bi-layer resist on the substrate; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to a T-gate opening; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to the shape of the club extension wherein the area corresponding to the club extension is approximately 1 micron to an ohmic source side of a T-gate and approximately 0.5 microns forward from a front of the T-gate; developing out the bi-layer resist in the exposed area that corresponds to the T-gate opening; developing out the bi-layer resist in the exposed area that corresponds to the club extension; and forming the T-gate and club extension through a metallization process.Type: GrantFiled: April 28, 2008Date of Patent: October 27, 2009Assignee: Northrop Grumman Space & Mission Systems Corp.Inventors: Carol Osaka Namba, Po-Hsin Liu, Ioulia Smorchkova, Michael Wojtowicz, Robert Coffie, Yaochung Chen