Abstract: A very compact package for an electronic data module, which includes battery-backed memory. A two-part metal container is used, which has two shallow concave pieces which fit together. The integrated circuit (in a low-height package, such as a flat-pack or SOIC) is mounted on a very small flexible printed circuit board, which fits inside the container. Laterally spaced from the integrated circuit, on the other end of the small flexible board, the board end is sandwiched between a battery and a piece of elastic conductive material (such as conductive plastic foam). Thus, the battery is connected between one face of the container and a power conductor on the board. The piece of elastic conductive material makes contact between a data trace on the board and the other face of the container. Another trace on the board makes contact directly to the container face on which the battery's ground terminal is connected.

Abstract: An integrated circuit filter wherein two digital inverters are used, with cutoff frequencies which bracket the desired passband frequency. (The cutoff frequency of the two digital inverters is selected by changing their RC time constants.) The inverter with the lower cutoff frequency has its output connected to the reset input of a counter, and the inverter with the higher cutoff-frequency has its output connected to the clock input of a counter.

Abstract: An integrated circuit which includes switching logic to select its negative power supply voltage from the more negative of two signals (preferably ground and an input signal). Special MOS clamp diodes are used to prevent sharp transients from collapsing the voltage drop of the internal power supply lines (and so disabling the chip).

Abstract: A secure electronic circuit which (in its early life) can be electronically calibrated and written to, but thereafter holds its data securely.

Abstract: An integrated circuit which includes a series resistor in the well tie. This resistor permits the wall to be used for clamping, without large current consumption due to the parastic bipolar device in the well.

Abstract: An integrated circuit which provides a low-power RS232 interface (or other serial interface). The integrated circuit receives separate power supply inputs for its own logic and for driving the serial line. Even if one of the power supply inputs fails, protection circuitry clamps floating nodes in the logic elements, and thereby avoids excessive current drain which might otherwise occur.

Abstract: An integrated circuit memory which includes at least some RAM/ROM hybrid columns. The RAM/ROM hybrid cells operate as normal SRAM cells forever, unless and until they are programmed to operate as ROM cells. Thus users who need the extra security permitted by ROM encoding can have this capability, while users who do not need ROM encoding can use off-the-shelf parts as RAM only.

Abstract: In a battery-powdered system, a first integrated circuit provides a secondary power supply to a second integrated circuit, and also provides data signals in a serial protocol. The first integrated circuit steps down the secondary power supply when the reset-bar signal is being driven high. The second chip goes active whenever its reset-bar input exceeds its battery-voltage input.

Abstract: A data communication system, including at least one base station and at least one portable module 120, wherein the portable module 120 transmits data on a high frequency, and the base station transmits data on a much lower frequency. Transmissions by the base station use a pulse-width modulation scheme where the most commonly used signals correspond to the shortest pulse. A "read" command is encoded as the same pulse width as one of the two write commands. Since the direction of data transmission is known in overhead, there will be no ambiguity.

Abstract: A very compact and economical electronic data module, which includes battery-backed memory. The module is preferably coin-shaped, and the two faces of the module are isolated from each other. The module contains logic to perform serial transfer of the whole memory content on command, using a one-wire bus.

Abstract: A multi-layer integrated circuit package uses split or bifurcated leads on separate levels, connected in parallel, for conducting the power supply voltages to an integrated circuit chip inside the package. The bifurcated leads are joined at the external pins of the package, and are split adjacent the die bond site of the package. The split ends provide separate power supply voltage conductors to the output driver circuitry on the integrated circuit chip and to the other circuitry in the integrated circuit chip. The effects of the transient currents induced in the power supply leads of the package are substantially isolated from the power supply voltages applied to the other circuitry of the integrated circuit chip.

Abstract: A low-power low-voltage CMOS six-transistor static random access memory (SRAM), which can operate on a power supply voltage which is less than the sum of the NMOS and PMOS threshold voltages, does not include any analog or metastable sense amplifier stages. The selected cell is allowed to pull one of its bitline pair all the way down to ground. Thus, full logic levels appear on the bitline pair. Only one line of the bitline pair is connected to the following gate stage. Preferably bitline precharge transistors are connected to always pull up any unselected bitline pair.

Abstract: An integrated circuit filter wherein two digital inverters are used, with cutoff frequencies which bracket the desired passband frequency. (The cutoff frequency of the two digital inverters is selected by changing their RC time constants.) The inverter with the lower cutoff frequency has its output connected to the reset input of a counter, and the inverter with the higher cutoff frequency has its output connected to the clock input of a counter.

Abstract: A RF receiver with extremely low standby power consumption. To minimize power consumption during standby, the analog input from the antenna circuit (including tank resonator) is connected directly to the inputs of a comparator.Preferably two comparators are used, each connected to a separate antenna. Thus, a signal loss due to antenna nulls will be minimized.Preferably a following stage decodes a pulse-width-modulated (or burst-length-modulated) signal. If the length of pulses substantially exceeds the expected maximum, the following stage provides a control signal to reduce the gain of the input comparators.

Abstract: An electronic key which responds to different sets of valid commands over its lifetime, depending on the state of certain circuits within the electronic key.(1) After initial fabrication of the electronic key, the electronic key recognizes a first set of valid commands and ignores all other commands.(2) After the electronic key is tested and a countdown circuit within the electronic key has been calibrated, a fusing element inside the electronic key is blown. This reduces the number of valid commands recognizable by the electronic key. Thus, the key is now restricted to a second set of valid commands.(3) The electronic key is then shipped to an OEM, who programs data into the key and also programs the length of time of the countdown timer. The OEM then sets an R-S flip-flop in the electronic key, which causes certain of the second set of commands to be ignored. Thus, the key will now respond only to a third set of valid commands.(4) The electronic key is then shipped to an end user.

Abstract: A dual port RAM includes an arbiter (10) which interfaces between a random access memory (12) and two ports, a serial port (19) and a parallel port (21). The arbiter (10) has an internal arbitration byte (38) for storing status information. The arbiter operates in first and second modes. In the first mode, the serial port (19) is afforded priority access to the system with status information stored in the arbitration byte (38). The parallel port (21) polls the arbitration byte (38) to determine the system status. In the second mode, the first port to attempt access is provided priority and this information is stored in the arbitration byte (38). In this mode, each port attempting access must poll the arbitration byte (38) before attempting access.

Abstract: A fusing and detection circuit includes a diode fusing element which is coupled to a fuse input terminal of an integrated circuit. Upon the application of the proper voltage at the fuse input terminal, the fuse element is blown, causing the diode to become a low impedance resistor. The detection circuitry senses whether the fuse has been blown or not and provides a lock or unlock indication at an output terminal. The fusing and detection circuit is designed to thwart attempts to change the lock status to an unlock status after the fuse has been blown.

Abstract: Registered output circuitry for a memory device includes a first latch which stores data from a sense amplifier on the rising edge, and outputs it on the falling edge, of the falling edge of an OE signal. This data stored in the latch is provided as output of only y, during the preceding rising edge of the OE signal the CE signal to the memory device was a logical 0 level, and the WE signal was a logical 1 level. Since the falling edge of the OE signal is the beginning of the memory cycle, the data at the output pin of the memory is the data read in the previous read cycle. This latency, however, enables a shortened average cycle time, and also provides registered outputs without the necessity of an external clock signal applied to the memory device.

Abstract: A remotely disposed RAM (12) is provided which is accessible by a centralized serial CPU (28) through a common data link. The RAM (12l ) is interfaced with the common data link through a serial port (19) and access thereto is controlled by an arbiter (10). The arbiter (10) includes a protocol shift register (31) for receiving control information, ID information and address information for the RAM (12). The ID information is compared with prestored identification information in an ID template (37). This ID template is operable to have a portion thereof masked off in response to receiving a mask command as part of the control information. If a match is present between the unmasked portion of the ID template and the corresponding portion of the ID information, access is allowed to the arbiter (10) and the RAM (12). A response is then transmitted to the common data link in the form of data read from the RAM.

Abstract: A micropowered module containing an integrated circuit packaged with a battery. The module is originally in a state of zero power consumption. When the module is to be put into use, a very strong electromagnetic field is applied at a predetermined frequency. A preset pulse code at this frequency will activate logic elements to keep the integrated circuit turned on, in active or standby mode. In standby mode, the power from the battery will avoid data loss.