Abstract: A timeout circuit with internal calibration includes an oscillator (11) for generating an initial frequency for division by a modulo-n counter (20). The counter (20) receives the value of n from a calibration register (22) and divides the frequency of the oscillator by the value of n. A gate (26) prevents alteration of the contents of the register (22). The output of the counter (20) provides a calibrated frequency which is further divided by a day counter (32) for output to a countdown counter (34). The countdown counter (34) provides a predetermined countdown of the signal output by the day counter (32) and, at the end of the count, generates a Timeout signal. The predetermined countdown value is determined by a value stored in a register (36) which can be protected by a customer lock out circuit (42).

Abstract: An electronic key which responds to different sets of valid commands over its lifetime, depending on the state of certain circuits within the electronic key,(1) After initial fabrication of the electronic key, the electronic key recognizes a first set of valid commands and ignores all other commands,(2) After the electronic key is tested and a countdown circuit within the electronic key has been calibrated, a fusing element inside the electronic key is blown. This reduces the number of valid commands recognizable by the electronic key. Thus, the key is now restricted to a second set of valid commands,(3) The electronic key is then shipped to an OEM, who programs data into the key and also programs the length of time of the countdown timer. The OEM then sets an R-S flip-flop in the electronic key, which causes certain of the second set of commands to be ignored. Thus, the key will now respond only to a third set of valid commands,(4) The electronic key is then shipped to an end user.

Abstract: A delay circuit which is insensitive to variations in power supply voltage, which is temperature-compensated, and which is suitable for fabrication in a monolithic integrated circuit includes circuitry for charging a capacitive element through a resistive element from GND toward the power supply voltage. The voltage across the capacitive element is compared to a reference voltage by a voltage comparator, and the voltage comparator generates an output signal when the voltage on the capacitor becomes greater than the reference voltage. The reference voltage for the comparator is generated by a resistor divider connected between GND and the power supply voltage. Inasmuch as the reference voltage varies with changes in the power supply voltage in such a manner as to be maintained at a substantially fixed percentage of the power supply voltage, the time delay provided by the delay circuit is essentially independent of variations in power supply voltage.

Abstract: A power controller for selectively coupling the voltage from a primary power source to a power output terminal or coupling the voltage from a battery backup input terminal to the power output terminal includes circuitry for receiving a reset or isolation signal. After receipt of the isolation signal when the primary power source is above a first threshold voltage, the primary power source and the backup battery source will be isolated from the output power terminal on the next occurrence of the removal of the voltage from the primary power source.

Abstract: A battery charging protection circuit for use in a power controller circuit utilizes the base emitter junction of a first NPN bipolar transistor to permit current to flow only from a backup battery input terminal to a power supply voltage output terminal of the power controller circuit. The base emitter junction and base collector junction of a second bipolar transistor are used to permit current to flow only in the direction from the backup battery input terminal to the substrate of the power controller circuit.

Abstract: An MOS capacitive structure comprising a substrate of a first conductivity type, a first region of the first conductivity type but having a different impurity concentration for contacting the substrate, a second region of opposite conductivity type for contacting the substrate, and a dielectric over a region of the substrate adjacent the first and second regions and having a conductive layer thereon forming one plate of the capacitor while the substrate opposite the conductive layer forms the other plate. The first and second regions are contacted and coupled together in order to provide good electrical contact to the substrate region opposite the conductive layer regardless of whether the substrate under the conductive layer is depleted or inverted.

Abstract: An electro-expulsive system 20 has one or more overlapped conductors OC1-OCN each comprising a flexible ribbon conductor 32 which is folded back on itself. The conductors are embedded in an elastomeric material 33. Large current pulses are fed to the conductors OC1-OCN from power storage units 1-N. As a result of the antiparallel currents I and I', the opposed segments of a conductor 32 are forcefully separated and the elastomeric material is distended. Void 34 in the elastomer aids the separation of the conductor segments. The distention is almost instantaneous when a current pulse reaches the conductor and the distention tends to remove any solid body on the surface of the elastomeric material.

Abstract: An integrated circuit having an option between two or more configurations and also using a patterned ion-implant for impressing data (such as a ROM section of the circuit) may advantageously perform the option-specification simultaneously with the ROM; using a powerless option-specifying circuit permits testing portions of the circuit before the implantation step.

Abstract: A ROM memory circuit featuring a bit line gain circuit to the output thereof, effective for establishing isolation of bit and output lines, reduction of bit line voltage swing, VREF level tracking and bit line select circuitry performing a logical OR between two adjacent column select signals with no more than three transistors and effective for generation of a sinking current to maximize the slew rate of the output signal nodes.

Abstract: A portable, non-volatile read/write memory module includes a battery for providing standby power that is coupled to a monolithic integrated circuit. Five terminals of the module are removably connected to a host electronic system for transfer of data to and from the module. One of the terminals is a chip enable input that may optionally be used for providing operating power to the monolithic integrated circuit. The monolithic integrated circuit further includes control circuitry that may optionally be coded for providing a security feature for access to data stored in the memory module.

Abstract: A transistor arrangement for clamping the output node of a semiconductor memory, including an inverter to parallel with a transmission gate for producing a differential output signal.

Abstract: CMOS reference voltage generation circuit comprising p- and n-channel MOS transistors in series from Vcc to ground having their gates and drains interconnected. The circuit includes transmission gates for isolating the reference voltage node, and a device for enhancing the slew rate of said node.

Abstract: A trip point clamping circuit for maintaining the voltage level at a node of connection to a sense arrangement including an inverter within defined bounds at the trip point of the inverter, the clamping circuit including a reference voltage, a source of similar current levels, a switch for turning the clamping circuit on and off, and a transistor responsive to the voltage level at said node of connection.

Abstract: An integrated circuit contains ROM, ROM patch and RAM memories on a common substrate with a standard pinout. The ROM and RAM fill the address space allowed by the address pins. Control of the patch memory without the use of special control pins is accomplished by writing to a ROM address with the standard control pins set for a RAM write. Various control functions are made of a series of standard-cycle read and write operations.

Abstract: A single stage operational amplifier voltage reference circuit for providing a precise reference voltage to bias multiple transistor-transistor logic (TTL) interface circuits is described. The voltage reference utilizes a current mirror having ratioed transistors to source or sink whatever current is necessary to maintain the reference voltage. The reference voltage is made substantially insensitive to process variations by ratioing transistor device sizes in a current source portion to transistor device sizes in an output load voltage divider portion. A capacitor is utilized to reduce transient errors at the output.

Abstract: An intrusion monitoring system includes an array of seismic sensors, such as geophones, arranged along a perimeter to be monitored for unauthorized intrusion as by surface movement or tunnelling. Two wires lead from each sensor to a central monitoring station. The central monitoring station has three modes of operation. In a first mode of operation, the output of all of the seismic sensors is summed into a receiver for amplification and detection. When the amplitude of the summed signals exceeds a certain predetermined threshold value an alarm is sounded. In a second mode of operation, the individual output signals from the sensors are multiplexed into the receiver for sequentially interrogating each of the sensors. Again, if the output from any one of the sensors exceeds a certain predetermined threshold value, a stop pulse is generated which stops the multiplexer at that sensor.

Abstract: A switched capacitor precision current source uses a capacitance to store a predetermined charge in response to a clock to provide an average current proportional to the frequency of the clock and the predetermined charge. The average current is useful for generating bias voltages for N channel and P channel current sources.

Abstract: A single slope analog to digital converter uses a DAC to trim the discharge current of a capacitor during calibration thereof. A method of calibrating the analog to digital converter is provided which iterates required steps to obtain a correct current setting within a short period of time. The analog to digital converter discharges a capacitor through a high impedance to obtain a linear discharge. The time to discharge the capacitor appears in a counter and is indicative of the voltage across the capacitor at the beginning of the discharge period once the analog to digital converter has been calibrated.

Abstract: A single chip MOS regulated negative power supply is comprised of first, second and third strings of field effect transistors and first and second amplifiers. The first string in conjunction with the zener diode develops a reference voltage which then passes through a voltage to current converter comprised of a first amplifier, the second string and an output transistor. The current thus produced passes through a third string of field effect transistors which is referenced to ground. The second amplifier provides negative feedback to the third string to produce the regulated output.

Abstract: The combination of a "C" mode scan electronics in a portable, battery powered biomedical ultrasonoscope having "A" and "M" mode scan electronics, the latter including a clock generator for generating clock pulses, a cathode ray tube having X, Y and Z axis inputs, a sweep generator connected between the clock generator and the X axis input of the cathode ray tube for generating a cathode ray sweep signal synchronized by the clock pulses, and a receiver adapted to be connected to the Z axis input of the cathode ray tube.