Abstract: A method for producing a semiconductor device using an improved trench isolation technique includes, first, forming a masking layer over a device layer. A first portion of the masking layer and an underlying portion of the device layer are removed to form at least one trench. A second portion of the masking layer is then selectively removed from a region adjacent the trench and above the device layer. A dielectric layer is formed in the trench so that the dielectric layer at least partially fills the trench and the region adjacent to the trench and above the device layer. The dielectric layer includes a trench cap above the trench isolation region and the device layer. The trench cap extends laterally and longitudinally above and beyond the trench isolation region, in accordance with the second portion of the masking layer which was removed.

Abstract: Dopant atoms have coefficients of diffusion that vary due to implant damage. Damaged regions are selected and created by implanting silicon atoms into a silicon substrate prior to formation of a gate electrode. The silicon atoms act as a getter for attracting selected dopants that are trapped in the silicon substrate. Dopants are implanted in the vicinity of the damaged regions and diffused by transient-enhanced diffusion (TED) into the damaged regions by thermal cycling to accumulate dopant atoms. Transient-enhanced diffusion improves the doping of a substrate by enhancing the diffusion of dopants at relatively low anneal temperatures. Dopant accumulation sets particular selected electrical properties without placing an excessive amount of dopant in regions adjacent to junctions for purposes including threshold control for a field device, threshold setting for a transistor, and prevention of device punchthrough.

Abstract: An improved method for planarizing an interlevel dielectric comprising two chemical mechanical polish steps. After an interlevel dielectric containing a topographical valley between a pair of topographical peaks is formed, the dielectric is chemically-mechanically polished in a first polish step at a first force using a first polish pad having a first rigidity to round the sharp dielectric corners or edges that exist at the transition between the peaks and valleys. After the first polish step has rounded the edges, a second polish step is performed with a second polish pad of second rigidity. The second polish pad is more rigid than the first polish pad and the second force is greater than the first. The second polish steps uses a high viscosity slurry to reduce slurry turnover in the regions proximate to the dielectric valleys thereby reducing the chemical etching in the valleys and improving the planarization efficiency.

Abstract: A method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths is disclosed. The method includes providing a semiconductor substrate with a first active region of a first conductivity type and a second active region of a second conductivity type, forming a first gate over the first active region and a second gate over the second active region, wherein the second gate has a substantially greater thickness than the first gate, forming first spacers in close proximity to opposing sidewalls of the first gate and second spacers in close proximity to opposing sidewalls of the second gate, wherein the second spacers have a substantially greater width than the first spacers due to the second gate having a substantially greater thickness than the first gate, and forming a first source and a first drain of the second conductivity type in the first active region and a second source and a second drain of the first conductivity type in the second active region.

Abstract: An IGFET with a gate electrode and metal spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, metal spacers adjacent to the sidewalls and the bottom surface, a gate insulator on the bottom surface between the metal spacers, protective insulators on the metal spacers, a gate electrode on the gate insulator and protective insulators, and a source and drain adjacent to the bottom surface.

Abstract: The present method provides for the detection and assessment of the net charge in a PECVD oxide layer deposited on a surface of a semiconductor substrate. Electrical potential differences across PECVD oxide layers on as-produced semiconductor substrates are measured. Resultant PECVD oxide charge derivative values are plotted on an control chart and compared to calculated control parameters. All measurement techniques are non-contact and non-destructive, allowing them to be performed on as-processed semiconductor substrates at any time during or following a wafer fabrication process. In a first embodiment, a contact potential difference V.sub.CPD between a vibrating electrode and the semiconductor substrate is measured while the semiconductor substrate beneath the vibrating electrode is subjected to a constant beam of high intensity illumination. The resultant value of V.sub.CPD is equal to the electrical potential difference across the PECVD oxide layer V.sub.OX (plus a constant).

Abstract: A fabrication process that produces an air gap dielectric in which a multi-level interconnect structure is formed upon a temporary supporting material. The temporary material is subsequently dissolved away leaving behind an intralevel and an interlevel dielectric comprised of air. In one embodiment of the invention, a first interconnect level is formed on a barrier layer. A temporary support material is then formed over the first interconnect level and a second level of interconnect is formed on the temporary support material. Prior to formation of the second interconnect level, a plurality of pillar openings are formed in the temporary material and filled with a conductive material. In addition to providing a contact between the first and second level of interconnects, the pillars provide mechanical support for the second interconnect level. The temporary material is dissolved in a solution that attacks the temporary material but leaves the interconnect material and pillar material intact.

Abstract: A shallow trench isolation structure and method for making the same are presented. In an embodiment, a trench dielectric is formed within a shallow trench that is disposed in a semiconductor substrate comprising single-crystalline silicon. Dielectric spacers are formed upon the opposed sidewall surfaces of a gate conductor arranged upon the semiconductor substrate a spaced distance from the trench dielectric. Formation of these dielectric spacers involves depositing a dielectric material across the semiconductor topography and anisotropically etching the dielectric material from horizontal surfaces more quickly than from the vertical sidewall surfaces of the gate conductor. Etch duration is terminated after a pre-defined lateral thickness of the dielectric material is achieved upon the sidewall surfaces of the gate conductor. The upper surface of the trench dielectric is also attacked by etchants during the formation of the dielectric spacers.

Abstract: A method for patterning an underlying metal substrate includes forming a layer of spin-on glass over the metal substrate, forming a layer of photoresist over the spin-on glass, patterning the photoresist, patterning the spin-on glass using the photoresist as a mask, and patterning the metal substrate by applying an etch using the spin-on glass as a hard mask wherein the etch removes the photoresist and partially removes the spin-on glass. In one embodiment, the spin-on glass is patterned by applying a fluorine-based plasma, an aluminum-based metal substrate is patterned by applying a chlorine-based plasma in which an etch selectivity of the metal substrate to the spin-on glass is at least 10:1, and the spin-on glass is removed by applying another fluorine-based plasma.

Abstract: An IGFET with source and drain contacts in close proximity to a gate with sloped sidewalls is disclosed. A method of making the IGFET includes forming a gate over a semiconductor substrate, wherein the gate includes a top surface, a bottom surface and opposing sidewalls, and the top surface has a substantially greater length than the bottom surface, forming a source and a drain that extend into the substrate, depositing a contact material over the gate, source and drain, and forming a gate contact on the gate, a source contact on the source, and a drain contact on the drain. The gate is separated from the source and drain contacts due to a retrograde slope of the gate sidewalls, and the gate contact is separated from the source and drain contacts due to a lack of step coverage in the contact material. Preferably, the contact material is a refractory metal, and the contacts are formed by converting the refractory metal into a silicide.

Abstract: A transistor with a buried insulative layer beneath a channel region is disclosed. Unlike conventional SIMOX, the buried insulative layer has a top surface beneath the channel region that is closer than bottom surfaces of the source and drain to the top surface of the substrate. Preferably, the buried insulative layer is formed by implanting oxygen into the substrate and then performing a high-temperature anneal so that the implanted oxygen reacts with silicon in the substrate to form a continuous stoichiometric layer of silicon dioxide. Advantageously, the buried insulative layer provides a diffusion barrier and an electrical isolation barrier for the channel region.

Abstract: A method of making an IGFET with a multilevel gate that includes upper and lower gate levels is disclosed. The method includes providing a semiconductor substrate with an active region, forming a gate insulator on the active region, forming a first gate material with a thickness of at most 1000 angstroms on the gate inslator and over the active region, forming a first photoresist layer over the first gate material, irradiating the first photoresist layer with a first image pattern and removing irradiated portions of the first photoresist layer to provide openings above the active region, etching the first gate material through the openings in the first photoresist layer using the first photoresist layer as an etch mask for a portion of the first gate material that forms a lower gate level, removing the first photoresist layer, forming an upper gate level on the lower gate level after removing the first photoresist layer, and forming a source and drain in the active region.

Abstract: An isolation technique is provided for improving the overall planarity of trench isolation regions relative to adjacent silicon mesas. The isolation process results in a spaced plurality of silicon risers formed in wide isolation regions. The space between silicon risers are ideally suited for optimal fill of a dielectric deposited across the semiconductor topography, i.e., across and between the silicon risers formed between active areas. The silicon risers, and optimally dimensioned trenches extending between the risers, enhance the planarity of the deposited dielectric. The deposited dielectric upper surface includes recesses of minimal elevational disparity, wherein the recesses are closely spaced in alignment directly above the trenches formed between silicon risers. The recesses can be readily removed by a chemical-mechanical polishing step with minimal deformity to the polishing pad, resulting in global planarization of the dielectric upper surface.

Abstract: A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a trench in the semiconductor substrate between said first active region and said second active region. A first dielectric layer is then formed on said trench and a polysilicon layer is deposited on said first dielectric layer. The polysilicon layer is then thermally oxidized to form a second dielectric layer. Preferably the first dielectric is a thermal oxide 40 to 500 angstroms in thickness consuming less than 200 angstroms of said first active region and said second active region. The polysilicon layer is preferably between 1000 to 2000 angstroms.

Abstract: A method of making the IGFET includes providing a semiconductor substrate, providing a gate over the semiconductor substrate, implanting lightly doped source and drain regions into the substrate, forming a source-side spacer and a drain-side spacer in close proximity to opposing sidewalls of the gate, forming a masking layer that covers the drain-side spacer and includes an opening over the source-side spacer, removing the source-side spacer, and implanting a heavily doped drain region and an ultra-heavily doped source region into the substrate after removing the source-side spacer while the drain-side spacer is present, wherein the heavily doped drain region is implanted through the masking layer and the ultra-heavily doped source region is implanted through the opening in the masking layer.

Abstract: An integrated circuit is provided having an improved interconnect structure. The interconnect structure includes a power-coupled local interconnect which is always retained at VDD or VSS (i.e., ground) level. The local interconnect resides a dielectric-spaced distance below critical runs of overlying interconnect. The powered local interconnect serves to sink noise transients from the critical conductors to ensure that circuits connected to the conductors do not inoperably function. Accordingly, the local interconnect extends along a substantial portion of the conductor length, and is either wider or narrower than the conductor under which it extends. The local interconnect can either be polysilicon, doped polysilicon, polycide, refractory metal silicide, or multi-level refractory metal.

Abstract: A method of doping an integrated circuit device channel in a semiconductor substrate laterally enclosed by an isolation structure is disclosed. The method includes steps of forming a thin oxide layer overlying the integrated circuit device channel and the isolation structure, depositing a polysilicon blanket layer overlying the thin oxide layer, patterning a photoresist mask overlying the polysilicon blanket layer and implanting dopant impurities into the polysilicon blanket layer. The method further includes steps of diffusing the dopant impurities from the polysilicon blanket layer through the thin oxide layer into the integrated circuit device channel, removing the polysilicon blanket layer, and removing the thin oxide layer.

Abstract: It has been discovered that different pattern densities that occur in conventional lithography produce a different final etch polysilicon gate width in high density (dense) regions of polysilicon gates as compared to low density (isolated) polysilicon gate regions. The final etch polysilicon gate width for a dense region is smaller by a predictable distance relative to the final etch polysilicon gate width for an isolated region. For example, a typical dense region has a final etch polysilicon gate width that is approximately 0.05 .mu.m smaller relative to the final etch polysilicon gate width of isolated regions having a channel length of 0.35 .mu.m. A biasing technique is employed for a polysilicon masking reticle in which the reticle is biased differently in regions of isolated polysilicon gates in comparison to regions of dense polysilicon gates.

Abstract: A resistor protect mask is used on a shallow trench isolation device junction to cover a device area except for a strip on the perimeter of the device area. The silicide layer formed on the central surface portion of the device and the strip area on the perimeter of the device upon which silicide formation is prevented forms a test structure for evaluation of junction formation that is immune from the effects of silicide formation on a device trench sidewall. Electrical tests and leakage measurements upon the test structure are compared directly to similar silicide shallow trench isolated devices which do not incorporate the resistor protect mask and shallow trench isolated devices without silicide to determine whether salicide processing is a cause of junction effects including junction leakage and short-circuiting.

Abstract: The present method provides for the detection and assessment of the net charge in a PECVD oxide layer deposited on a surface of a semiconductor substrate. Electrical potential differences across PECVD oxide layers on as-produced semiconductor substrates are measured. Resultant PECVD oxide charge derivative values are plotted on an control chart and compared to calculated control parameters. All measurement techniques are non-contact and non-destructive, allowing them to be performed on as-processed semiconductor substrates at any time during or following a wafer fabrication process. In a first embodiment, a contact potential difference V.sub.CPD between a vibrating electrode and the semiconductor substrate is measured while the semiconductor substrate beneath the vibrating electrode is subjected to a constant beam of high intensity illumination. The resultant value of V.sub.CPD is equal to the electrical potential difference across the PECVD oxide layer V.sub.OX (plus a constant).