Abstract: A photolithographic system includes individually controllable radiation sources for forming an image pattern on an image plane without using a reticle or mask during fabrication of an integrated circuit device. The radiation sources are selectively activated as they scan the image plane. The image pattern can consist of parallel lines having identical widths and varying lengths, or alternatively, pixels having identical shapes and sizes. The radiation sources can be arranged as a linear array, or a staggered array, to achieve the desired linear density. Suitable radiation sources include light pipes, light emitting diodes, and laser diodes. Preferably, each of the activated radiation sources provides an exposure field of less than 0.1 microns on the image plane, and at least two of the radiation sources must be activated to provide the minimum line width of the image pattern.

Abstract: Each circuit block of a plurality of circuit blocks on a semiconductor substrate is imaged in an exposure field defined by a reticle. The circuit blocks are separated and electrically isolated within the semiconductor substrate by an isolation such as a field oxide or trench isolation. The circuit blocks are globally interconnected by depositing a blanket metal layer, masking the metal layer and etching the metal layer using a stitching reticle having an exposure field overlapping the plurality of circuit blocks. The combination of reticle-imaged circuit blocks allows each individual circuit block to be fabricated independently, using independent imaging resolution, layout rules, design rules, different polysilicon sizes and source/drain region sizes and the like. In addition different reticles, including different reticle types, resolutions and qualities may be used to construct the various circuit blocks.

Abstract: An isolation technique is provided for improving the overall planarity of trench isolation regions relative to adjacent silicon mesas. The isolation process results in a spaced plurality of field dielectric having an upper surface substantially coplanar with each other and with adjacent silicon mesa upper surfaces. The isolation process is thereby a planarization process used with the shallow trench technique, wherein etch-enhancing ions are forwarded into the fill dielectric at upper elevational regions of that dielectric. When subjected to a subsequent etchant, the dopants cause the higher elevational regions to be removed at a faster rate than the lower elevational regions. Thus, selective placement of dopants and etch removal pre-conditions the fill dielectric upper surface to a more planar surface globally across the entire wafer.

Abstract: A method of making NMOS and PMOS devices with different gate lengths includes providing a semiconductor substrate with first and second active regions, forming a first gate over a portion of the first active region and a second gate over a portion of the second active region, wherein the first and second gates are formed in sequence and have different lengths, and forming a source and drain in the first active region and a source and drain in the second active region. Preferably, the first gate is defined by a first photoresist layer patterned with a first exposure time, the second gate is defined by a second photoresist layer patterned with a second exposure time, and the difference in gate lengths is due primarily to a difference between the first and second exposure times.

Abstract: A multilevel interconnect structure is provided. The multilevel interconnect structure includes at least three levels of interconnect (conductors) formed according to one exemplary embodiment. Two of the three levels of conductors are staggered from each other in separate vertical and horizontal planes. A third conductor is advantageously spaced a lateral distance between at least a portion of two second conductors. The third conductor is also placed in an elevational level below or possibly above the second conductor so as to reduce the capacitive coupling therebetween. By staggering the second and third conductors, high density interconnect can be achieved with minimal propagation delay and cross coupling.

Abstract: Disclosed is an improved method and apparatus for removing tough, inedible skin and underlying fat from a frozen fish such as tuna, marlin, shark, and swordfish. The apparatus includes a high speed, contoured rotary cutter disposed in a housing with a tailored aperture through which is exposed a limited sector portion of the cutter. The apparatus is manually applied to the frozen fish and traversed across the fish in a series of passes to effectively and efficiently denude the fish of substantially all of the skin and fat. A depth of cut guide precludes burrowing of the cutter into the comestible flesh thereby maintaining high yield.

Abstract: A reduced permittivity interlevel dielectric in a semiconductor device arranged between two levels of interconnect. The dielectric comprises a first dielectric layer preferably from a silane source deposited on a first level interconnect to form air gaps at midpoints between adjacent first interconnect structures, a second dielectric containing air gap trenches at spaced intervals across the second dielectric, and a third dielectric formed upon said second dielectric. A second interconnect level is formed on the third dielectric.

Abstract: An IGFET with a gate electrode and metal spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, metal spacers adjacent to the sidewalls and the bottom surface, a gate insulator on the bottom surface between the metal spacers, protective insulators on the metal spacers, a gate electrode on the gate insulator and protective insulators, and a source and drain adjacent to the bottom surface.

Abstract: A reduced permittivity interlevel dielectric is provided. The interlevel dielectric is formed between two levels of interconnect. The interlevel dielectric comprises a first dielectric layer formed from a TEOS source deposited on a first level interconnect. The first dielectric contains air gaps at spaced intervals across the first dielectric. A second dielectric, preferably from a silane source is deposited upon said first dielectric. A second interconnect level is then placed on the second dielectric.

Abstract: An improved multilevel interconnect structure is provided. The interconnect structure includes pillars spaced from each other across a wafer. The pillars are placed between levels of interconnect or between an interconnect level and a semiconductor substrate. The pillars are spaced from each other by an air gap, such that each conductor within a level of interconnect is spaced by air from one another. Furthermore, each conductor within one level of interconnect is spaced by air from each conductor within another level of interconnect. Air gaps afford a smaller interlevel and intralevel capacitance within the multilevel interconnect structure, and a smaller parasitic capacitance value affords minimal propagation delay and cross-coupling noise of signals sent through the conductors.

Abstract: Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source.

Abstract: A dielectric material is provided having air gaps which form during dielectric deposition between horizontal or vertical spaced conductors. The dielectric is deposited upon a polyimide, wherein the polyimide is placed over and between an underlying level of conductors. As the overlying dielectric is deposited on the polyimide, the polyimide material outgasses to form air separation between the polyimide and dielectric. Air separation is particularly prevalent in regions between closely spaced conductors and in high elevational areas directly above each conductor. The dielectric deposition process preferably includes two deposition cycles. A first deposition temperature is used to force significant outgassing, and a second deposition cycle is needed to close any and all keyhole openings which might exist between closely spaced conductors.

Abstract: A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply.

Abstract: A subfield conductive layer is provided, wherein a conductive layer is implanted beneath and laterally adjacent a field dielectric. The subfield conductive layer is placed within the silicon substrate after the field dielectric is formed. The conductive layer represents a buried interconnect which resides between isolated devices. The buried interconnect, however, is formed using high energy ion implant through a field dielectric formed either by LOCOS or shallow trench isolation techniques. The buried interconnect, or conductive layer, resides and electrically connects source and drain regions of two isolated devices.

Abstract: A method of forming a recessed interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween.

Abstract: An asymmetrical IGFET including a lightly and heavily doped drain regions and an ultra-heavily doped source region is disclosed. Preferably, the lightly doped drain region and ultra-heavily doped source region provide channel junctions.

Abstract: A dielectric material is provided having air gaps which form during dielectric deposition between interconnects. The dielectric is deposited in interconnect-spaced geometries which have certain aspect ratios and which are exposed at the bottom of the geometries to a hygroscopic dielectric. During deposition, the dielectric is forced along the sidewall of the spaced interconnects as a result of moisture ougasing from the hygroscopic dielectric. Over a period of time, a keyhole occurs with pile up accumulation (or cusping) at the corners of the spaced interconnects. By decreasing the deposition temperature in a subsequent step, outgasing is minimized, and deposition over the keyhole and upon the hygroscopic dielectric takes place. Keyhole coverage results in an air gap which is surrounded on all sides by the fill dielectric. Air gap between interconnects helps reduce permittivity of the overall dielectric structure, resulting in a lessening of the interconnect line-to-line capacitance.

Abstract: A resistor protect mask is used on a shallow trench isolation device junction to cover a device area except for a strip on the perimeter of the device area. The silicide layer formed on the central surface portion of the device and the strip area on the perimeter of the device upon which silicide formation is prevented forms a test structure for evaluation of junction formation that is immune from the effects of silicide formation on a device trench sidewall. Electrical tests and leakage measurements upon the test structure are compared directly to similar silicide shallow trench isolated devices which do not incorporate the resistor protect mask and shallow trench isolated devices without silicide to determine whether salicide processing is a cause of junction effects including junction leakage and short-circuiting.

Abstract: A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply.

Abstract: A method of inspecting a lens includes projecting a first amount of radiation through a first test pattern and the lens to provide a first lens error associated with a first heating of the lens, projecting a second amount of radiation through a second test pattern and the lens to provide a second lens error associated with a second heating of the lens, and using the first and second lens errors to provide image displacement data that varies as a function of heating the lens. In this manner, corrections can be made for localized lens heating that is unique to a given reticle. The method is well-suited for photolithographic systems such as step and repeat systems.