Abstract: A material for use in a magnetic resonance system includes a carrier material and a doping material. The carrier material and the doping material are admixed in a specific proportion. A volume of the material smaller than 1 mm2 contains a substantially homogeneous intermixing of the carrier material and the doping material.

Abstract: Apparatus and systems, as well as methods and articles, may operate to detect an input/output access operation associated with a configuration memory address and a first memory address bit size. The configuration memory address and associated configuration data may be combined into a packet having a second memory address bit size (e.g., 64 bits) greater than the first memory address bit size (e.g., 32 bits). The packet may be used to establish compatibility for legacy operating systems that attempt to communicate with peripheral component interconnect (PCI) interface-based peripherals, and similar platform devices, that have been integrated into the same package as the processor.

Abstract: Methods and apparatus to operate various logic blocks of an integrated circuit (IC) at independent voltages are described. In one embodiment, supply of power to one or more domains in an IC is adjusted based on an indication that power consumption by components of the corresponding domain is to be modified. Other embodiments are also described.

Abstract: The operating voltage of an integrated circuit (e.g., a processor) is changed in response to one or more conditions (e.g., a laptop computer is connected to an AC power source). Both the operating frequency and the operating voltage of the integrated circuit are changed. The voltage regulator providing the operating voltage to the integrated circuit is caused to transition between voltage levels using one or more intermediate steps. The integrated circuit continues to operate in the normal manner both at the new voltage and throughout the voltage transition.

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Abstract: A system is disclosed. The system includes a central processing unit (CPU) to operate in one or more low power sleep states, and a power converter. The power converter includes phase inductors; and one or more power switches to drive the phase inductors. The one or more power switches are deactivated during the CPU sleep state.

Abstract: The invention relates to a metal/plastic hybrid and to a shaped body produced therefrom. By combining metallic additives in plastic, it has been shown for the first time that specific volume resistances of less than 10?2 ?cm can be realized while the compounds have, at the same time, a good processability during the injection molding process.

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Abstract: The invention relates to flexible compounds that are made of a thermoplastic elastomer and a filler having increased thermal conductivity, and to flexible heat-conducting tubes produced on the basis thereof that are especially useful as heating or cooling tubes. The inventive mixtures have a thermal conductivity in the range of from 0.5 to 2 W/mK.

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Abstract: The operating voltage of an integrated circuit (e.g., a processor) is changed in response to one or more conditions (e.g., a laptop computer is connected to an AC power source). Both the operating frequency and the operating voltage of the integrated circuit are changed. The voltage regulator providing the operating voltage to the integrated circuit is caused to transition between voltage levels using one or more intermediate steps. The integrated circuit continues to operate in the normal manner both at the new voltage and throughout the voltage transition.

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Abstract: The operating voltage of an integrated circuit (e.g., a processor) is changed in response to one or more conditions (e.g., a laptop computer is connected to an AC power source). Both the operating frequency and the operating voltage of the integrated circuit are changed. The voltage regulator providing the operating voltage to the integrated circuit is caused to transition between voltage levels using one or more intermediate steps. The integrated circuit continues to operate in the normal manner both at the new voltage and throughout the voltage transition.

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Abstract: A system is disclosed. The system includes a central processing unit (CPU) to operate in one or more low power sleep states, and a power converter. The power converter includes phase inductors; and one or more power switches to drive the phase inductors. The one or more power switches are deactivated during the CPU sleep state.

Abstract: A detector to detect the magnitude of the jitter that may occur in a first clock signal and a second clock signal and to generate an alarm signal if the magnitude of the jitter exceeds the threshold value. The detector comprises a one-hot register storing a one-hot value comprising a first logic bit (=1) centered around one or more second logic bits (=0). The detector comprises a threshold register storing a threshold value comprising one or more second logic bits centered around one or more first logic bits. An event of a first clock rotates the contents of the one-hot value and an event of a second clock rotates the contents of the threshold value. A match between the pre-specified bit of the one-hot value and the threshold value indicates the occurrence of the jitter having a magnitude greater than the threshold value.

Abstract: Methods and apparatus to improve integrated circuit (IC) performance across a range of operating conditions and/or physical constraints are described. In one embodiment, an operating parameter of one or more of processor cores may be adjusted in response to a change in the activity level of processor cores (e.g., the number of active processor cores) and/or a comparison of one or more operating conditions and one or more corresponding threshold values. Other embodiments are also described.

Abstract: A method and apparatus for current detection for microelectronic devices using source-switched sensors. An embodiment of a current detector for a microelectronic device includes a first voltage sensor and a second voltage sensor. The first voltage sensor is to measure a first voltage of the microelectronic device during a first time period and a second voltage of the microelectronic device during a second time period. The second voltage sensor is to measure the second voltage during the first time period and the first voltage during the second time period. A voltage value is equal to the sum of the first voltage measured by the first sensor plus the first voltage measured by the second sensor, minus the sum of the second voltage measured by the first sensor plus the second voltage measured by the second sensor. Other embodiments are also described and claimed.