Abstract: provides SOI CMOS technology whereby a polysilicon back-gate is used to control the threshold voltage of the front-gate device, and the nMOS and pMOS back-gates are switched independently of each other and the front gates. Specifically, the present invention provides a method of fabricating a back-gated fully depleted CMOS device in which the device's back-gate is self-aligned to the device's front-gate as well as the source/drain extension. Such a structure minimizes the capacitance, while enhancing the device and circuit performance. The back-gated fully depleted CMOS device of the present invention is fabricated using existing SIMOX (separation by ion implantation of oxygen) or bonded SOI wafer bonding and thinning, polySi etching, low-pressure chemical vapor deposition and chemical-mechanical polishing.

Abstract: An integrated circuit, such as a memory macro, includes multiple power rails supporting first and second voltage differentials, with the second voltage differential being smaller than the first voltage differential. Signal lines in the integrated circuit are driven with the small voltage swing, which is generated by small swing circuits. The integrated circuit further includes regeneration circuits, which are receiving small voltage swing inputs and are outputting first, or full voltage swings. The application of the small voltage swing to the signal lines saves power in the integrated circuit. A wide bandwidth, full-wordline I/O, memory integrated circuit has simultaneously operable connection paths between essentially all the memory cells that are attached to the same wordline and the corresponding I/O terminals, and it has a single ended data-line structure.

Abstract: A radiation detector formed using silicon-on-insulator technology. The radiation detector includes a silicon layer formed on an insulating substrate, wherein the silicon layer includes a PNPN structure, and a gate layer formed over the PNPN structure, wherein the gate layer includes a PN gate. Latch-up occurs in the radiation detector only in response to incident radiation.

Abstract: A random access memory (RAM) circuit is coupled to a write control line, a read control line, and one or more bitlines, and includes a write switch having a control terminal and first and second terminals. The first terminal of the write switch is coupled to the one or more bitlines, and the control terminal of the write switch is coupled to the write control line. The circuit includes a charge-storage device having first and second terminals, wherein a first terminal of the charge-storage device is coupled to the second terminal of the write switch and a second terminal of the charge-storage device is coupled to the read control line. The circuit includes a read switch having a control terminal and first and second terminals. The control terminal of the read switch is coupled to the first terminal of the charge-storage device and is coupled to the second terminal of the write switch.

Abstract: A carrier for a semiconductor component is provided having passive components integrated in its substrate. The passive components include decoupling components, such as capacitors and resistors. A set of connections is integrated to provide a close electrical proximity to the supported components.

Abstract: Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.

Abstract: A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided. The SOI MOSFET device includes a polysilicon back-gate which controls the threshold voltage of a polysilicon-containing front-gate. The back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.

Abstract: A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided in which an implanted back-gate is formed into a Si-containing layer of an SOI wafer. The implanted back-gate thus formed is capable of controlling the threshold voltage of a polysilicon-containing front-gate which is formed over a portion of the implanted back-gate region. The implanted back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.

Abstract: A carrier for a semiconductor component is provided having passive components integrated in its substrate. The passive components include decoupling components, such as capacitors and resistors. A set of connections is integrated to provide a close electrical proximity to the supported components.

Abstract: Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.

Abstract: A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided. The SOI MOSFET device includes a polysilicon back-gate which controls the threshold voltage of a polysilicon-containing front-gate. The back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.

Abstract: A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided in which an implanted back-gate is formed into a Si-containing layer of an SOI wafer. The implanted back-gate thus formed is capable of controlling the threshold voltage of a polysilicon-containing front-gate which is formed over a portion of the implanted back-gate region. The implanted back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.

Abstract: A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided. The SOI MOSFET device includes a polysilicon back-gate which controls the threshold voltage of a polysilicon-containing front-gate. The back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.

Abstract: A method and system are disclosed for adjusting the threshold in MOS devices, in particular for devices used in DRAM sense amplifiers. The effects of process and temperature variations on the threshold are compensated by a back-bias voltage. A comparison of an indicating voltage and a reference voltage is used to generate the back-bias voltage. The direction of back-bias voltage may be either in the backward, or in the forward bias direction.

Abstract: A method and system are disclosed for adjusting the threshold in MOS devices, in particular for devices used in DRAM sense amplifiers. The effects of process and temperature variations on the threshold are compensated by a back-bias voltage. A comparison of an indicating voltage and a reference voltage is used to generate the back-bias voltage. The direction of back-bias voltage may be either in the backward, or in the forward bias direction.

Abstract: Disclosed is a high speed sense amplifier circuit designed for sensing data in one-transistor DRAM memory cells on bit lines within DRAM macros. The circuit utilizes a charge transfer scheme to rapidly remove charge from a small sensing first capacitor C1, generating a voltage swing delta V1, via an FET operating in its subthreshold region by means of idling current, such transfer supplying an equal charge to the larger bit line capacitance Cb1 with small voltage swing delta Vb1. The sense amp is pre-charged to the “1” state, and senses a “0” via the charge transfer operation thusly described. A “1” is sensed when no charge transfer takes place.

Abstract: Disclosed is a high speed sense amplifier circuit designed for sensing data in one-transistor DRAM memory cells on bit lines within DRAM macros. The circuit utilizes a charge transfer scheme to rapidly remove charge from a small sensing first capacitor C1, generating a voltage swing delta V1, via an FET operating in its subthreshold region by means of idling current, such transfer supplying an equal charge to the larger bit line capacitance Cb1 with small voltage swing delta Vb1. The sense amp is pre-charged to the “1” state, and senses a “0” via the charge transfer operation thusly described. A “1” is sensed when no charge transfer takes place.

Abstract: A short cycle DRAM use a floating wordline, dynamic row decoder and bitline VDD precharge, which improves the array efficiency of the short cycle DRAM (3-6 ns) without compromising its performance. A small size wordline driver circuit is provided to reduce the row size of the short cycle DRAM without compromising row access timing. A dynamic decoding operation is implemented which intentionally allows some of the deselected wordlines to float during row access. A Vdd bitline precharge/sensing technique avoids a detrimental (or positive) coupling effect to the floating wordlines during row accessing. A Vdd data-line (or DQ) precharge for a read operation, and control of incoming data timing avoids a detrimental (or positive) coupling effect for a write operation.

Abstract: In a DRAM memory circuit, a current sensing amplifier is provided that exploits the low impedance of a reference transistor biased in the sub-threshold regime to enable transfer of a small voltage swing on the bitline to result in a large voltage signal on a low capacitance sense node. Compared to conventional voltage sensing, reduced bitline-bitline coupling noise results because of the small bitline swing, potentially allowing more cells to be served by a sense amplifier because of weak dependence of sense amplifier on bit-line capacitance. Compared to previous current-sensing schemes, this invention allows no idling current. The current-sensing amplifier additionally may be used in conjunction with a hierarchical bitline scheme to further increase the number of cells served by each sense amplifier.

Abstract: A method for fabricating silicon on insulator structures having a dislocation free silicon layer. The method utilizes low temperature UHVCVD to deposit a very heavily doped etch stop layer having a very steep doping profile onto a substrate and a lightly doped active layer onto the etch stop layer. An insulator is formed on the active layer and a carrier wafer is formed on the insulator layer. The original substrate is removed in a first etch and the etch stop layer is removed in a second etch resulting in a thin, uniform active layer. In one embodiment, a small percentage of germanium is added to the etch stop layer to produce a defect free epitaxial active layer.