Abstract: A semiconductor memory is described incorporating an energy conserving cyclic power source for charging and discharging the bit line with a minimum voltage across the switches. The invention overcomes the problem of power dissipation in a semiconductor memory due to charging and discharging capacitances to a voltage supply or to ground. The cyclic power supply produces a slowly varying waveform to drive the bit lines or other lines in a memory array such as a dynamic RAM in a manner so that the energy stored on those lines or in the cyclic power source is recovered at the end of the cycle.

Abstract: A method for fabricating silicon on insulator structures having a dislocation free silicon layer. The method utilizes low temperature UHVCVD to deposit a very heavily doped etch stop layer having a very steep doping profile onto a substrate and a lightly doped active layer onto the etch stop layer. An insulator is formed on the active layer and a carrier wafer is formed on the insulator layer. The original substrate is removed in a first etch and the etch stop layer is removed in a second etch resulting in a thin, uniform active layer. In one embodiment, a small percentage of germanium is added to the etch stop layer to produce a defect free epitaxial active layer.

Abstract: The interface circuit of the present invention adjusts the signal voltage across a leaking transistor such that the leakage is reduced while also shunting out the adjustment means when the adjustment means impedes the operation of the interface circuit. One embodiment of the present invention is a level translator comprised of a level shifting stage coupled to a buffer stage. The level shifting stage has its power source coupled to a current shunting device. The current shunting device is connected in parallel across the first P-channel device of the level shifting stage. The first P-channel device of the level shifting stage is connected in series with a second P-channel device having its drain connected to a drain of a first N-channel device wherein the first N-channel device has its source connected to a drain of a second N-channel device. The current shunting device is formed from a single P-channel device.

Abstract: An off-chip driver circuit which includes a complementary pair of field effect transistor source followers connected in a non-inverting series circuit arrangement. The driver circuit includes an n-channel device to pull the output up to the positive supply less the threshold drop across the device and a p-channel device to pull the output down for the opposite transition to within a threshold voltage drop above ground of the p-channel device. The driver circuit includes means for eliminating body effect by connecting the n(p)-well of the p(n) channel transistor to the output node. The driver circuit provides a reduced swing low noise output which reduces the collapse of the power supply. The driver circuit provides an appropriate impedance match to the output transmission line, so that the output transmission line can be terminated to eliminate reflections.

Abstract: Lightly Depleted PMOS (LDP) substrate-plate trench-capacitor (SPT) cell Array architecture is disclosed including three types of devices: An enhancement NMOS transistor (ENMOS) which has a n+ poly gate with a positive threshold voltage range, an enhancement PMOS transistor (EPMOS) having a p+ poly gate with a negative threshold voltage range, and a lightly depleted PMOS transistor (LDPMOS) having a p+ poly gate. The LDPMOS is used as the access transistor in the SPT cell with body biased at the power supply voltage VDD, and can also be used in the write drivers. A sense amplifier is included which is a CMOS cross-coupled latch. An n-well is biased at a lower voltage than VDD, such as (VDD--Vg) where Vg is the silicon bandgap, and the lower thresholds enhance faster sensing. The CMOS cross-coupled latch is activated by turning on latching devices.

Abstract: A semiconductor substrate which contains a buried grid-like region of enhanced concentration of an impurity type opposite to that of the semiconductor substrate; and method for the fabrication thereof which includes providing beneath the upper surface of a semiconductor substrate at a first depth a continuous region of a first impurity type which is the same as that of the semiconductor substrate and wherein at preselected isolated discontinuous locations beneath said surface the first impurity type is at a second depth beneath said surface which is greater than said first depth, and then providing beneath said first depth and substantially coincident with said second depth, a second impurity type opposite to that of the first type and at a dosage level lower than the dosage level of the first impurity type so as to provide a grid-like region of enhanced concentration of impurity type opposite to that of the semiconductor substrate for collecting excess minority carriers in the semiconductor substrate.

Abstract: A one-device, FET dynamic random access memory array is disclosed wherein a problem arising from the short-channel effect is reduced in single-polysilicon, one-device field effect transistor dynamic random access memory arrays where a portion of a word line is used as an electrode of a memory cell storage capacitor. When such word lines are accessed, boosted voltages can appear across the source-drain of FET devices of unaccessed memory cells causing them to conduct and spuriously lose information. This problem is minimized in such memory arrays by opening a pair of bit line switches so that the potential on an unselected bit line remains at the potential to which it was precharged. In this manner, the potential difference across the source-drain of the FETs of unselected memory cells can never exceed the potential to which all the bit lines are precharged.

Abstract: A fabrication method is disclosed for providing self-aligned (i.e., misregistration tolerant or "borderless") contact vias for electrical connections between metal interconnection lines and underlying doping semiconductive regions of an integrated circuit. The described method utilizes an oxidation barrier layer material which is patterned twice to provide, first, the recessed oxide isolation regions and, later, the self-aligned contact vias. An example of an n-channel FET embodiment is described wherein self-aligned contact vias are provided between aluminum interconnection lines and n-type doped source and drain regions. In the described method, at least a portion of the normally present misregistration region or border is eliminated between the boundary of a recessed isolation oxide and the boundary of the via. The latter is ultimately coincident with the boundary of an underlying doped region.

Abstract: A field effect transistor (FET) with a unique gate structure is disclosed wherein the polycrystalline silicon (polysilicon) gate is self-aligned on its ends with respect to the conductive source and drain regions, and is self-aligned on its sides with respect to the nonconductive field isolation regions. The boundaries of these conductive and nonconductive regions determine the boundaries of the channel region of the FET. This double self-alignment feature results in a polysilicon gate, the lateral dimensions and location of which correlate directly with the lateral dimensions and location of the channel region of the FET. The unique gate fabrication technique employed according to the present invention comprises delineating lithographic patterns twice in the same polysilicon layer using the same oxidation barrier masking layer; whereby the first lithographic pattern delineates the FET device regions, and the next lithographic pattern forms the gate regions wherever the two patterns cross each other (i.e.

Abstract: A field effect transistor (FET) wherein the field insulator is nonrecessed with respect to the source and drain regions, wherein the sides of the polysilicon gate electrode are self-aligned with respect to the nonconductive field insulator and neither overlap nor underlap the field insulator. The lateral dimensions and location of the gate correlate directly with the lateral dimensions and location of the channel region of the FET. The gate fabrication technique employed comprises delineating lithographic patterns twice in the same polysilicon layer; whereby the first lithographic pattern delineates regions to be used for sources and drains, and the next lithographic pattern forms the gate regions.

Abstract: A differential charge transfer amplifier which functions as a sensing and regenerating circuit responsive to binary information represented by the level of charge in a stored charge memory cell is disclosed. The sense amplifier includes a pair of dummy cells and bucket brigade amplifiers which are connected on either side of a dynamic latching circuit which includes a plurality of actuable gate devices, which may be field effect transistors. A bit/sense line of the array is divided into two equal sections which are respectively connected to either side of the sense amplifier. The operation of the amplifier is cyclic, including a precharge period, a sensing period, a rewrite period and a restore period, after which the amplifier is in its original state. A feature of the amplifier is that it consumes no d.c. power other than leakage and has high sensitivity due to a charge transfer feature.