Abstract: A semiconductor device includes: a trench formed in a surface of a semiconductor substrate and extending lengthwise in a direction parallel to the surface; a body region adjoining the trench; a source region adjoining the trench above the body region; a drift region adjoining the trench below the body region; a field electrode in a lower part of the trench and separated from the substrate; and a gate electrode in an upper part of the trench and separated from the substrate and the field electrode. A first section of the field electrode is buried below the gate electrode in the trench. A second section of the field electrode transitions upward from the first section in a direction toward the surface. The separation between the second section and the gate electrode is greater than or equal to the separation between the first section and the gate electrode.

Abstract: A semiconductor device includes a vertical power transistor having a plurality of power transistor cells. Each power transistor cell includes a source region at a first main surface of a semiconductor substrate, a drain region at a second main surface of the semiconductor substrate opposite the first main surface, a gate trench extending into the semiconductor substrate from the first main surface, a gate electrode in the gate trench and comprising doped polycrystalline silicon, and a dielectric material separating the gate electrode from the semiconductor substrate. An upper central part of each of the gate electrodes of the power transistor cells is occupied by a metal silicide region that adjoins the doped polycrystalline silicon. A method of producing the semiconductor device is also described.

Abstract: A semiconductor device includes: a semiconductor substrate; an epitaxial layer or layer stack on the semiconductor substrate; a plurality of transistor cells of a first type formed in a first region of the epitaxial layer or layer stack and electrically coupled in parallel to form a vertical power transistor; a plurality of transistor cells of a second type different than the first type and formed in a second region of the epitaxial layer or layer stack; and an isolation structure that laterally and vertically delimits the second region of the epitaxial layer or layer stack. Sidewalls and a bottom of the isolation structure include a dielectric material that electrically isolates the plurality of transistor cells of the second type from the plurality of transistor cells of the first type in the epitaxial layer or layer stack. Methods of producing the semiconductor device are also described.

Abstract: Embodiments are disclosed for display configurations for providing an augmented reality heads-up display. In one or more examples, a heads-up display device includes at least one display and the heads-up display updates sizes and positions of virtual objects multiple times for each image that is captured via a camera. The virtual objects may be updated based on a trajectory of an object in the real-world.

Abstract: A semiconductor device includes: a semiconductor substrate; an epitaxial layer or layer stack on the semiconductor substrate; a plurality of transistor cells of a first type formed in a first region of the epitaxial layer or layer stack and electrically coupled in parallel to form a vertical power transistor; a plurality of transistor cells of a second type different than the first type and formed in a second region of the epitaxial layer or layer stack; and an isolation structure that laterally and vertically delimits the second region of the epitaxial layer or layer stack. Sidewalls and a bottom of the isolation structure include a dielectric material that electrically isolates the plurality of transistor cells of the second type from the plurality of transistor cells of the first type in the epitaxial layer or layer stack. Methods of producing the semiconductor device are also described.

Abstract: A multi-chip assembly includes: a first power transistor die having a source terminal facing a first direction and a drain terminal facing a second direction opposite the first direction; and a second power transistor die having a drain terminal facing the first direction, and a source terminal facing the second direction. A dielectric material occupies a gap between the first power transistor die and the second power transistor die, and secures the first power transistor die and the second power transistor die to one another. A metallization connects the source terminal of the first power transistor die to the drain terminal of the second power transistor die at a same side of the multi-chip assembly. The gap occupied by the dielectric material is less than 70 ?m. Corresponding methods of producing multi-chip assemblies are also described.

Abstract: A semiconductor device is described. The semiconductor device includes: a semiconductor substrate having a first main surface; a plurality of gate trenches extending from the first main surface into the semiconductor substrate; a semiconductor mesa between adjacent gate trenches; a first interlayer dielectric on the first main surface; a plurality of first metal contacts extending through the first interlayer dielectric and contacting gate electrodes disposed in the gate trenches; a plurality of second metal contacts extending through the first interlayer dielectric and contacting the semiconductor mesas; and an air gap or a dielectric material having a lower dielectric constant than the first interlayer dielectric between adjacent first and second metal contacts. Methods of producing the semiconductor device are also described.

Abstract: Methods and systems are provided for a device for a communications control system. In one example, the device includes a distributed component interconnect framework (DCIF) configured to enable communication between different software modules of a communications network based on already existing code. The DCIF allows simultaneous communication between multiple transport protocols.

Abstract: A semiconductor device includes: a semiconductor substrate; a plurality of transistors cells in an active device region of the semiconductor substrate, each transistor cell having a gate electrode separated from the semiconductor substrate by a gate dielectric; a plurality of needle-shaped field plate trenches in the active device region and in a termination region of the semiconductor substrate that is devoid of fully functional transistor cells; a polysilicon layer that forms the gate electrodes in the active device region and extends over at least part of the termination region; and a shielding layer that separates the polysilicon layer from the semiconductor substrate in the termination region, the shielding layer having a higher dielectric strength than just the gate dielectric. A method of producing the semiconductor device is also described.

Abstract: A semiconductor die includes: a silicon substrate; a trench gate NMOS transistor formed in a first device region of the silicon substrate; a trench gate PMOS transistor formed in a second device region of the silicon substrate and electrically connected to the trench gate NMOS transistor; and an isolation structure interposed between the first device region and the second device region. Methods of monolithically integrating the trench gate NMOS transistor and the trench gate PMOS transistor in the same semiconductor die are also described.

Abstract: Methods and systems are provided for a device for a communications control system. In one example, the device includes a distributed component interconnect framework (DCIF) configured to enable communication between different software modules of a communications network based on already existing code. The DCIF allows simultaneous communication between multiple transport protocols.

Abstract: A power semiconductor device includes: trench gate structures in an active cell region of a semiconductor substrate and extending into an inactive cell region of the semiconductor substrate that adjoins the active cell region; an electrically insulating material covering the trench gate structures; first contact openings in the electrically insulating material between adjacent trench gate structures in the active cell region; second contact openings in the electrically insulating material vertically aligned with the trench gate structures in the inactive cell region; first counter-doped regions between the adjacent trench gate structures in the active cell region and vertically aligned with the first contact openings; second counter-doped regions underneath the trench gate structures in the inactive cell region and vertically aligned with the second contact openings; first contacts in the first contact openings; and second contacts in the second contact openings.

Abstract: A semiconductor device is described. The semiconductor device includes: a semiconductor substrate having a first main surface; a plurality of gate trenches extending from the first main surface into the semiconductor substrate; a semiconductor mesa between adjacent gate trenches; a first interlayer dielectric on the first main surface; a plurality of first metal contacts extending through the first interlayer dielectric and contacting gate electrodes disposed in the gate trenches; a plurality of second metal contacts extending through the first interlayer dielectric and contacting the semiconductor mesas; and an air gap or a dielectric material having a lower dielectric constant than the first interlayer dielectric between adjacent first and second metal contacts. Methods of producing the semiconductor device are also described.

Abstract: Methods and systems are provided for a device for a communications control system. In one example, the device includes a distributed component interconnect framework (DCIF) configured to enable communication between different software modules of a communications network based on already existing code. The DCIF allows simultaneous communication between multiple transport protocols.

Abstract: A semiconductor device includes: a semiconductor substrate; an epitaxial layer or layer stack on the semiconductor substrate; a plurality of transistor cells of a first type formed in a first region of the epitaxial layer or layer stack and electrically coupled in parallel to form a vertical power transistor; a plurality of transistor cells of a second type different than the first type and formed in a second region of the epitaxial layer or layer stack; and an isolation structure that laterally and vertically delimits the second region of the epitaxial layer or layer stack. Sidewalls and a bottom of the isolation structure include a dielectric material that electrically isolates the plurality of transistor cells of the second type from the plurality of transistor cells of the first type in the epitaxial layer or layer stack. Methods of producing the semiconductor device are also described.

Abstract: A semiconductor device is described. The semiconductor device includes: a Si substrate having a first main surface; a plurality of gate trenches extending from the first main surface into the Si substrate; a semiconductor mesa between adjacent gate trenches; a first interlayer dielectric on the first main surface; a plurality of first metal contacts extending through the first interlayer dielectric and contacting gate electrodes disposed in the gate trenches; a plurality of second metal contacts extending through the first interlayer dielectric and contacting the semiconductor mesas; and an air gap or a dielectric material having a lower dielectric constant than the first interlayer dielectric between adjacent first and second metal contacts. Methods of producing the semiconductor device are also described.

Abstract: In an embodiment, a semiconductor device includes a vertical power FET for switching a load current, the power FET including a channel region of a first conductivity type and a first lateral FET and a second lateral FET providing an output stage of gate driver circuitry for driving the power FET. The first lateral FET includes a channel region of the first conductivity type and the second lateral FET includes a channel region of a second conductivity type opposing the first conductivity type. The power FET and the first and second lateral FETs are monolithically integrated into a semiconductor substrate of the first conductivity type and that has a first surface. A drain of the first lateral FET and a source of the second lateral FET are electrically coupled to a gate of the power FET.

Abstract: In an embodiment, a semiconductor device is provided that includes: a vertical power FET configured to switch a load current and provide a channel of a first conductivity type; and a lateral FET configured to drive the vertical power FET and provide a channel of a second conductivity type opposing the first conductivity type. The vertical power FET and the lateral FET are monolithically integrated into a semiconductor substrate of the first conductivity type and a drain of the lateral FET is electrically coupled to a gate of the vertical power FET.

Abstract: A multi-chip assembly includes: a first power transistor die having a source terminal facing a first direction and a drain terminal facing a second direction opposite the first direction; and a second power transistor die having a drain terminal facing the first direction, and a source terminal facing the second direction. A dielectric material occupies a gap between the first power transistor die and the second power transistor die, and secures the first power transistor die and the second power transistor die to one another. A metallization connects the source terminal of the first power transistor die to the drain terminal of the second power transistor die at a same side of the multi-chip assembly. The gap occupied by the dielectric material is less than 70 ?m. Corresponding methods of producing multi-chip assemblies are also described.

Abstract: A semiconductor device includes a source region and a drain region of a first conductivity type, a body region of a second conductivity type between the source region and the drain region, a gate configured to control current through a channel of the body region, a drift zone of the first conductivity type between the body region and the drain region, a superjunction structure formed by a plurality of regions of the second conductivity type laterally spaced apart from one another by intervening regions of the drift zone, and a diffusion barrier structure disposed along sidewalls of the regions of the second conductivity type of the superjunction structure. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si.