Abstract: An apparatus is disclosed for thermal desorption of contaminants from contaminated material, the apparatus including: a plurality of first insulated boxes, each insulated box, defining a volume effective for holding contaminated material, and each insulated box defining an opening at the top of the insulated box; at least one top effective to fit on the opening at the top of the insulated box and each top defining a pattern of heater orifices; a plurality of heaters, the heaters being insertable into the volume for holding contaminated material, through the heater orifices defined by the top; and a vapor extraction system effective to-remove vapors from within the volume for holding contaminated material.

Abstract: A continuous process is provided for preparing silica microgels using carbon dioxide as a gel initiator at a pressure of at least about 172 kPa (about 25 psig). Consistent performance of microgel can be produced with varying production rates.

Abstract: To allow accurate positioning relative to a printer mechanism, a printhead is provided with a reference surface formed on a reference member. The reference member is attached to the base of the printhead but positioned with reference to a nozzle of an ink ejecting unit mounted on the base member. This obviates the need for the base member to be manufactured to narrow tolerances.

Abstract: An inductive component includes a substrate on the surface of which is a lower insulation layer having a shallow concavity or trench, a first plurality of conductive elements formed in the trench, a magnetic core formed over the first plurality of conductive elements, and a second plurality of conductive elements formed over the core. The first and second pluralities of conductive elements are connected to each other so as to form an inductive coil around the core. First and second core insulation layers are disposed between the core and the first and second pluralities of conductive elements, respectively. The component is fabricated by a method in which it is built up in the trench using thin film techniques. A first array of conductors is patterned over the lower insulation layer, and a first core insulation layer is applied over the first conductor array. A magnetic core is formed on top of the first core insulation layer, and a second core insulation layer is applied over the core.

Abstract: A laser marking device for marking a reference point with laser light so that accurate measurements can be made to that point. The laser marking device includes a support bar that has first and second ends and a longitudinal axis extending between the first and second ends. The first and second ends are adapted to slidably rest on the horizontal portions of an adjacent pair of T-bars of a suspended ceiling. An illuminating device emits a beam of light to illuminate a reference point. The illuminating device is slidably mounted to the support bar.

Abstract: A system for dislodging by-product agglomerations from a polishing pad of a chemical mechanical polishing (CMP) machine. The present invention is used in conjunction with a CMP machine that polishes semiconductor wafers. Specifically, an embodiment of the dislodging system in accordance with the present invention includes a megasonic nozzle which is adapted to effectively dislodge polishing by-product agglomerations and particles from the grooves and micro-pits of the surface of a polishing pad through the application of an output stream of extremely agitated fluid (e.g., deionized water). One embodiment of the megasonic nozzle in accordance with the present invention includes two piezoelectric transducers which operate at a resonant frequency to produce the extremely agitated stream of fluid. A fluid line is connected to the megasonic nozzle and a fluid source in order to convey fluid to the megasonic nozzle.

Abstract: A test device and method for determining parameters of a plurality of vias formed into a dielectric material making contact to a buried conductive layer. The present invention is comprised of a sample structure disposed within the material through which a plurality of vias are to be formed. The sample structure is adapted to enhance secondary electron yield from the via bottom during a scanning electron microscope examination of the vias. Additionally, the plurality of vias to be formed are disposed intentionally offset with respect to the sample structure. As a result, the enhanced secondary electron yield from the sample structure characterizes the degree of misalignment present in the via formation process. In so doing, the present invention simultaneously quantifies the critical dimension of the vias, the alignment/registration of the via formation process, and determines whether or not the vias are etched to a minimum desired depth.

Abstract: A process for making an integrated circuit is disclosed. This technique includes electrically interconnecting a pair of adjacent transistors positioned along a semiconductor substrate by coating with an oxide layer, planarizing the layer, then forming a trench exposing a contact region for each transistor. This trench is filled with a metal, such as tungsten to provide an electrical interconnection of the contact regions. The metal is then planarized to be approximately coplanar with the planarized oxide layer. Metal gate electrodes are formed at the same time as the interconnection. Additional processing includes depositing an IMO layer over the planarized metal and oxide and defining additional interconnections through the IMO layer.

Abstract: A process is provided which can be used, for example, to clarify substantially aqueous fluids and separate solids from the fluid. The process comprises combining the fluid with a composition which comprises an anionic silica-based colloid having an S value of less than 50% and a cationic organic polymer.

Abstract: A test device and method for determining parameters of a plurality of vias formed into a dielectric material making contact to a buried conductive layer. The present invention is comprised of a sample structure disposed within the material through which a plurality of vias are to be formed. The sample structure is adapted to enhance secondary electron yield from the via bottom during a scanning electron microscope examination of the vias. Additionally, the plurality of vias to be formed are disposed intentionally offset with respect to the sample structure. As a result, the enhanced secondary electron yield from the sample structure characterizes the degree of misalignment present in the via formation process. In so doing, the present invention simultaneously quantifies the critical dimension of the vias, the alignment/registration of the via formation process, and determines whether or not the vias are etched to a minimum desired depth.

Abstract: A process is provided which can be used to clarify substantially aqueous streams and optionally separate biosolids, especially proteins, from food processing operations which comprises contacting an aqueous stream comprising biosolids with an anionic inorganic colloid and an organic polymer, to flocculate the biosolids.

Abstract: A semiconductor device structure and method for producing a shaped etch-front during an etching process. In one embodiment, the present invention is comprised of a first layer of material which is disposed above a contact layer. In this embodiment, the first layer of material has a first etch rate. Next, the present invention deposits a second layer of material above at least a portion of the first layer of material. The second layer of material has a second etch rate which is faster than the first etch rate. Additionally, in the present invention, the first layer of material and the second layer of material have a sloped interfacial topography. The sloped interfacial topography of the present invention creates shaped etch-front during the etching of an opening extending through the first layer of material and the second layer of material.

Abstract: An isolation structure on an integrated circuit is formed using a shallow trench isolation process. A layer of buffer oxide is formed on a substrate. A layer of nitride is formed on the layer of buffer oxide. The layer of nitride and the layer of buffer oxide are patterned to form a trench area. The substrate including the trench area is subjected to a plasma comprising H.sub.2 O vapor, and a gaseous fluorocarbon or a fluorinated hydrocarbon gas to clean impurities on the trench area. The substrate is etched to form a trench within the trench area.

Abstract: A gate region of a transistor is prepared for receiving a deposit of metal. A chemical mechanical polishing process is performed to reduce thickness of an insulation layer above the gate region. At the end of the chemical mechanical polishing process, a portion of the insulating layer remains above the gate region. An etch process is performed to remove the portion of the insulating layer remaining above the gate region. The etch process also removes a portion of polysilicon within the gate region and removes a top portion of spacers on either side of the gate region. A polysilicon selective etch-back is performed to remove an additional portion of the polysilicon within the gate region.

Abstract: A system for framing a canopy has a carrier sheet and a coating of adhesive deposited onto the carrier sheet. A transparent film is cast over the coating of adhesive, and the film defines a plurality of slits configured for forming frames or masks which conform to the shape of the canopy. Alternatively, in a method for framing a canopy having interior and exterior sides, a first coat of paint having a first color is applied onto a first side of a transparent film, and a second coat of paint having a second color is applied onto the first coat of paint. A second side of the film is then adhered to the exterior side of the canopy so that the first coat of paint is visible on the interior side of the canopy, and the second coat of paint is visible on the exterior side of the canopy.

Abstract: Silica deposits formed during a continuous process for preparing polysilicate microgel are removed and purged form the process by elastically deforming the vessel walls, reducing plugging.

Abstract: Modified starches prepared by cooking an amphoteric or cationic starch and an anionic, amphoteric, or cationic polyacrylamide have utility as a retention aid in the manufacture of paper.

Abstract: Modified starches prepared by cooking an amphoteric or cationic starch and certain polyacrylamides have improved performance in paper making if a soluble aluminum compound also is present.

Abstract: A method for preventing oxygen microloading of an SOG layer. In one embodiment of the present invention, hydrogen is introduced into an etching environment. An etching step is then performed within the etching environment. During the etching step an SOG layer overlying a TEOS layer is etched until at least a portion of the underlying TEOS layer is exposed. The etching step continues and etches at least some of the exposed portion of the TEOS layer. During etching, the etched TEOS layer releases oxygen. The hydrogen present in the etching environment scavenges the released oxygen. As a result, the released oxygen does not microload the SOG layer. Thus, the etchback rate of the SOG layer is not significantly affected by the released oxygen, thereby allowing for controlled etchback of the SOG layer.

Abstract: A method of isolating a semiconductor device by shallow trench isolation is provided by: (a) etching a trench into the surface of an integrated circuit; (b) depositing an oxide in the trench so that at least the upper portion of the oxide is silicon-rich; (c) providing a polysilicon gate electrode on the surface of the integrated circuit, with the gate electrode being provided substantially adjacent to the trench with a space between the trench and the gate electrode; (d) providing a spacer oxide to cover the trench oxide, the gate electrode and the space between the trench and the gate electrode, so that the spacer oxide has near-stoichiometric levels of silicon; and (e) etching the spacer oxide from the surface of the integrated circuit under conditions effective to selectively etch the spacer oxide from the upper surface of the integrated circuit and from the upper surface of the gate electrode without etching the trench oxide from the upper portion of the trench.