Abstract: One embodiment of the present invention provides a system that facilitates reducing the power needed for proximity communication. This system includes an integrated circuit with an array of transmission pads that transmit a signal using proximity communication. A layer of fill metal is located in proximity to this array of transmission pads, wherein the layer of fill metal is “floating” (e.g., not connected to any signal). Leaving this layer of fill metal floating reduces the parasitic capacitance for the array of transmission pads, which can reduce the amount of power needed to transmit the signal.

Abstract: Embodiments of the present invention provide a system that electronically aligns mini-bars on different semiconductor chips which are situated face-to-face to facilitate communication between the semiconductor chips through capacitive coupling. During operation, the system selects a group of transmitter mini-bars on the first chip to form a transmitter bit position and selects a group of receiver mini-bars on the second chip to form a receiver bit position. The system then associates transmitter bit positions on the first chip with proximate receiver bit positions on the second chip. In this way, the system allows data signals transmitted by the mini-bars within a transmitter bit position on the first chip to be collectively received by the mini-bars within an associated receiver bit position on the second chip.

Abstract: A multiplying delay-locked loop (MDLL) is described. In the MDLL, a phase interpolator (PI) provides a correction signal to selection control logic by phase mixing two internal signals (which have different phases) from a sequence of delay elements in the MDLL. This correction signal compensates for a delay associated with the selection control logic, thereby ensuring that a selection pulse or signal output by the selection control logic to a selection circuit (such as a multiplexer) is appropriately timed so that the selection circuit can selectively injection lock the sequence of delay elements using edges in a reference signal.

Abstract: A method of testing a proximity communication system for voltage margin by impressing a voltage upon the data link between the transmitter on one chip and the receiver on the other chip coupled to the transmitter through a capacitively coupling circuit formed by juxtaposed capacitor pads on the respective two chips. The impressed voltage is varied and the output of the receiver is monitored to determine an operational voltage margin. The floating inputs on the receiver may be continuously biased by connecting them to variable biasing supply voltages through high impedances. When the floating inputs are periodically refreshed to a refresh voltage during a quiescent data period, the refresh voltage is varied between successive refresh cycles. The variable test voltage may be applied to transmitter output when it is in a high-impedance state, and the output of the receiver is measured.

Abstract: A repeater circuit, such as a clock regeneration and multiplication circuit, is described. In this repeater circuit, a clock multiplier unit (CMU) generates an internal clock signal based on a forwarded clock signal, which is received on a link. Furthermore, a phase interpolator (PI) in the repeater circuit provides the output clock signal based on the forwarded clock signal and the internal clock signal. Note that the CMU and the PI filter reduce the cycle-to-cycle jitter in the forwarded clock signal and the internal clock signal, and that the output clock signal has a phase that is a weighted average of the phases of the forwarded clock signal and the internal clock signal. In addition, the relative weights of the forwarded clock signal and the internal clock signal (i.e., the amount of phase averaging and jitter filtering) may be adjusted based on a position or location on the link.

Abstract: One embodiment of the present invention provides an integrated circuit chip, including an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. The integrated circuit chip additionally comprises an electromagnetic via that facilitates communication between signal pads on the integrated circuit chip and signal pads on a second integrated circuit chip. The electromagnetic via couples a signal pad on the active face of the integrated circuit chip to the back face of the integrated circuit chip so that the integrated circuit chip can communicate with the second integrated circuit chip while the back face of the integrated circuit chip is adjacent to the active face of the second integrated circuit chip. Moreover, the electromagnetic via operates by facilitating non-conductive signaling through the integrated circuit chip.

Abstract: One embodiment of the present invention provides a system that automatically detects and corrects a misalignment of a semiconductor chip. During operation, the system uses a position-detection mechanism integrated with the chip to determine the misalignment of the chip from a desired alignment for the chip. Next, the system uses an actuation mechanism integrated with the chip to automatically correct the misalignment, thereby improving performance and reliability of the chip.

Abstract: A multiplying delay-locked loop (MDLL) is described. In the MDLL, a phase interpolator (PI) provides a correction signal to selection control logic by phase mixing two internal signals (which have different phases) from a sequence of delay elements in the MDLL. This correction signal compensates for a delay associated with the selection control logic, thereby ensuring that a selection pulse or signal output by the selection control logic to a selection circuit (such as a multiplexer) is appropriately timed so that the selection circuit can selectively injection lock the sequence of delay elements using edges in a reference signal.

Abstract: A semiconductor die is described. This semiconductor die includes an electro-static discharge (ESD) device with a metal component coupled to an input-output (I/O) pad, and coupled to a ground voltage via a signal line. Moreover, adjacent edges of the metal component and the I/O pad are separated by a spacing that defines an ESD gap. When a field-emission or ionization current flows across the ESD gap, the metal component provides a discharge path to the ground voltage for transient ESD signals. Furthermore, the ESD gap is at least partially enclosed so that there is gas in the ESD gap.

Abstract: One embodiment of the present invention provides an integrated circuit chip, including an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. The integrated circuit chip additionally comprises an electromagnetic via that facilitates communication between signal pads on the integrated circuit chip and signal pads on a second integrated circuit chip. The electromagnetic via couples a signal pad on the active face of the integrated circuit chip to the back face of the integrated circuit chip so that the integrated circuit chip can communicate with the second integrated circuit chip while the back face of the integrated circuit chip is adjacent to the active face of the second integrated circuit chip. Moreover, the electromagnetic via operates by facilitating non-conductive signaling through the integrated circuit chip.

Abstract: A phase-interpolator circuit is described. In the phase-interpolator circuit, an output signal, having a fundamental frequency and a phase, is generated based on a weighted summation of a first reference signal and a second reference signal, where the first reference signal has the fundamental frequency and a first phase, and the second reference signal has the same fundamental frequency and a second phase. Note that contributions of the first reference signal and the second reference signal, respectively, to the output signal are determined based on associated first and second impedance values in a weighting circuit in the phase-interpolator circuit. For example, a programmable capacitance ratio of two capacitors may be used to interpolate between the first reference signal and the second reference signal.

Abstract: A chip package is described. This chip package includes a stack of semiconductor dies or chips that are offset from each other, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, electrically couples to the exposed pads. For example, the ramp component may be electrically coupled to the semiconductor dies using: microsprings, an anisotropic film, and/or solder. Consequently, the electrical contacts may have a conductive, a capacitive or, in general, a complex impedance. Furthermore, the chips and/or the ramp component may be positioned relative to each other using a ball-and-pit alignment technique. By removing the need for costly and area-consuming through-silicon vias (TSVs) in the semiconductor dies, the chip package facilitates chips to be stacked in a manner that provides high bandwidth and low cost.

Abstract: A processing technique facilitating the fabrication of the integrated circuit with microsprings at different vertical positions relative to a surface of a substrate is described. During the fabrication technique, microsprings are lithographically defined on surfaces of a first substrate and a second substrate. Then, a hole is created through a first substrate. Moreover, the integrated circuit may be created by rigidly mechanically coupling the two substrates to each other such that the microsprings on the surface of the second substrate are within a region defined at least in part by an edge around the hole. Subsequently, photoresist that constrains the microsprings on the surfaces of the two substrates may be removed. In this way, microsprings at the different vertical positions can be fabricated.

Abstract: An optical connector is described. This optical connector spatially segregates optical coupling between an optical fiber and an optical component, which relaxes the associated mechanical-alignment requirements. In particular, the optical connector includes an optical spreader component disposed on a substrate. This optical spreader component is optically coupled to the optical fiber at a first coupling region, and is configured to optically couple to the optical component at a second coupling region that is at a different location on the substrate than the first coupling region. Moreover, the first coupling region and the second coupling region are optically coupled by an optical waveguide.

Abstract: A circuit that receives input signals from a transmitter via proximity communication, such as capacitively coupled proximity communication, is described. Because proximity communication may block DC content, the circuit may restore the DC content of input signals. In particular, a refresh circuit in the circuit may short inputs of the circuit to each other at least once per clock cycle (which sets a null value). Furthermore, a feedback circuit ensures that, if there is a signal transition in the input signals during a current clock cycle, it is passed through to an output node of the circuit. On the other hand, if there is no signal transition in the input signals during the current clock cycle, the feedback circuit may select the appropriate output value on the output node based on the output value during the immediately preceding clock cycle.

Abstract: Embodiments of a switch are described. This switch includes input ports configured to receive signals (which include data) and output ports configured to output the signals. In addition, the switch includes switching elements and a flow-control mechanism, which is configured to provide flow-control information associated with the data to the switching elements via an electrical control path. Note that the electrical control path is configured to use proximity communication to communicate the flow-control information. Furthermore, the switching elements are configured to selectively couple the input ports to the output ports via optical signal paths based on the flow-control information.

Abstract: One embodiment of the present invention provides a system that facilitates high-bandwidth communication using a flexible bridge. This system includes a chip with an active face upon which active circuitry and signal pads reside, and a second component with a surface upon which active circuitry and/or signal pads reside. A flexible bridge provides high-bandwidth communication between the active face of the chip and the surface of the second component. This flexible bridge provides a flexible connection that allows the chip to be moved with six degrees of freedom relative to the second component without affecting communication between the chip and the second component. Hence, the flexible bridge allows the chip and the second component to communicate without requiring precise alignment between the chip and the second component.

Abstract: Embodiments of a circuit for use with an inter-chip connection that has a variable complex impedance (which can be conductive, capacitive or both), a system that includes the circuit, and a communication technique are described. This inter-chip connection may be formed between a microspring or an anisotropic film and a metal connector on or proximate to a surface of a chip. Moreover, the circuit may mitigate signal distortion associated with the variable complex impedance. For example, the circuit may include an internal impedance that is electrically coupled in series with the metal connector, and that has an impedance which dominates the variable complex impedance over a range of operating frequencies. Separately or additionally, the circuit may be adapted to correct for the signal distortion.

Abstract: Embodiments of a system are described. This system includes an array of single-chip modules (CMs), which includes a first CM and a second CM which are coupled to each other. A given CM, which can be either the first CM or the second CM, includes a semiconductor die that is configured to communicate data signals with other CMs by capacitively coupled proximity communication and optical proximity communication using proximity connectors. These proximity connectors are proximate to a surface of the semiconductor die, and the semiconductor die includes an optical signal path configured to communicate on-chip optical signals.

Abstract: A system that fabricates a semiconductor chip. The system places patterns for components which require fine line-widths within a high resolution region of a reticle, wherein the high resolution region provides sharp focus for a given wavelength of light used by the lithography system. At the same time, the system places patterns for components which do not require fine line-widths outside of the high-resolution region of the reticle, thereby utilizing the region outside of the high-resolution region of the reticle instead of avoiding the region. Note that the coarseness for components placed outside of the high resolution region of the reticle is increased to compensate for the loss of optical focus outside of the high resolution region.