Abstract: A film-to-video format detector (24) for a digital television receiver (10). The detector (24) receives pixel data from a current field and a second preceding field. It determines a set of pixel difference values, sums them to obtain a field difference value, and compares the field difference value to a threshold. These steps are repeated to obtain a series of field difference indicators. This series is analyzed to determine whether it has a pattern corresponding to a film-to-video format.

Abstract: There is disclosed a multiprocessor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories are contained on a single silicon chip. Each processor can operate to execute the same instruction at the same time (SIMD mode) or different instructions at the same time (MIMD mode).

Abstract: A SLM-based projection display system (10) samples and processes video data for delivery to a spatial light modulator (SLM) (13c), and uses a color wheel (14a) to color the SLM-generated images. A frame memory (13b) provides data to the SLM (13c) and is managed so that, if the phase of the incoming video signal changes, a desired phase relationship between the color wheel position and the data available to the SLM (13c) can be maintained. Also, a motor control unit (15a) uses a horizontal sync signal to generate a drive signal for the color wheel motor (16a), which limits the transient time during phase-changing events, and which provides a means for adjusting the phase of the drive signal.

Abstract: A color separator (12) for a digital television receiver (10). The incoming television signal is directed to two different paths in the color separator (12). Along a first path, the luminance component is separated by an analog Y separator (12a) and then sampled by an A/D converter (12b) at a rate that will provide a desired number of samples per display line. Along a second path, the composite signal is sampled by an A/D converter (12c) at a rate appropriate for digital color separation, and then the chrominance samples are separated using a digital C separator (12d). A scaling unit (12e) then scales the chrominance samples to provide a desired number of samples per line.

Abstract: A multi-processor system and method arranged, in one embodiment, as an image and graphics processor. The multiprocessor system includes several individual processors all having communication links to several memories. Additional instruction memories are dedicated individually as cache memories to particular processors so that the processors can function in the multiple instruction, multiple data (MIMD) mode. When the processors function in the single instruction, multiple data mode (SIMD) the dedicated memories are reassigned for access by all of the processors for data. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.

Abstract: There is disclosed a switch matrix and operational method relying upon a high degree of operational logic at each matrix crosspoint. In one embodiment, the switch is used in a multiprocessor system arranged as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. The switch matrix serves to establish the processor memory links and the entire image processor, including the individual processors, the crossbar switch and the memories and is contained on a single silicon substrate.

Abstract: There is disclosed a multiprocessor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories are contained on a single silicon chip. Each processor can operate to execute the same instruction at the same time (SIMD mode) or different instructions at the same time (MIMD mode).

Abstract: There is disclosed a device and method for providing signals representative of the positional altitude of a user. The device is responsive to hand or head movements to move a dampened substance contained within a confined tube past one or more sensors. Light passing through the tube is interrupted by the movement of the dampened substance which can be a liquid or a solid object within a viscous liquid.

Abstract: A system detects scene changes in a sequence of video images by analyzing the sequence for abrupt frame-to-frame changes in certain image features. The system accepts the signal into a quantizer, which digitizes the image, and stores it into a frame buffer. An image processor, a component of the system, analyzes the digitized images, and determines certain features which a decision processor can use to detect a scene change.

Abstract: The disclosure relates to a method and system for improving the cosmetic appearance of a display responsive to signals from a CCD wherein the locations of defects in the CCD are located and stored and wherein, upon scanning of a defective pixel in the CCD, a comparison is made and sucessive succeeding signals to the display are not altered while defective pixel addresses continue to be addressed.