Patents by Inventor Robert J. Hayes

Robert J. Hayes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • GENETIC LOCUS IMPARTING A LOW ANATABINE TRAIT IN TOBACCO AND METHODS OF USING
    Publication number: 20240117371
    Abstract: Provided herein are genetic markers and a coding sequence associated with a low- or ultra-low anatabine trait in tobacco.
    Type: Application
    Filed: December 4, 2023
    Publication date: April 11, 2024
    Applicant: ALTRIA CLIENT SERVICES INC.
    Inventors: Chengalrayan KUDITHIPUDI, Alec J. HAYES, Robert Frank HART, III, Yanxin SHEN, Jesse FREDERICK, Dongmei XU
  • Method, apparatus and system for configuring a protocol stack of an integrated circuit chip
    Patent number: 10282341
    Abstract: Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Peripheral Component Interconnect Express™ (PCIe™) specification. Configuration circuitry of the IC chip provides for configuration of a first protocol stack including the transaction layer, circuitry of the link layer and a first physical layer of the IC chip. The configuration circuitry further provides for an alternative configuration of a second protocol stack including the transaction layer, circuitry of the link layer and a second physical layer of the IC chip. In another embodiment, the first protocol stack supports single-ended signaling to communicate TLP information, whereas the second protocol stack supports differential signaling to communicate TLP information.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: May 7, 2019
    Assignee: Intel Corporation
    Inventors: Bryan L. Spry, Marcus W. Song, Deepak M. Rangaraj, Avinash N. Ananthakrishnan, Robert J. Hayes, Aimee D. Wood, Adam E. Letendre, Brent R. Boswell
  • Optimized Fc variants and methods for their generation
    Patent number: 10183999
    Abstract: The present invention relates to optimized Fc variants, methods for their generation, and antibodies and Fc fusions comprising optimized Fc variants.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: January 22, 2019
    Assignee: Xencor, Inc.
    Inventors: Gregory Alan Lazar, Arthur J. Chirino, Wei Dang, John Desjarlais, Stephen K. Doberstein, Robert J. Hayes, Sher Bahadur Karki, Omid Vafa
  • Optimized Fc variants and methods for their generation
    Patent number: 10184000
    Abstract: The present invention relates to optimized Fc variants, methods for their generation, and antibodies and Fc fusions comprising optimized Fc variants.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: January 22, 2019
    Assignee: Xencor, Inc.
    Inventors: Gregory Alan Lazar, Arthur J. Chirino, Wei Dang, John Desjarlais, Stephen K. Doberstein, Robert J. Hayes, Sher Bahadur Karki, Omid Vafa
  • METHOD, APPARATUS AND SYSTEM FOR CONFIGURING A PROTOCOL STACK OF AN INTEGRATED CIRCUIT CHIP
    Publication number: 20180210857
    Abstract: Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Peripheral Component Interconnect Express™ (PCIe™) specification. Configuration circuitry of the IC chip provides for configuration of a first protocol stack including the transaction layer, circuitry of the link layer and a first physical layer of the IC chip. The configuration circuitry further provides for an alternative configuration of a second protocol stack including the transaction layer, circuitry of the link layer and a second physical layer of the IC chip. In another embodiment, the first protocol stack supports single-ended signaling to communicate TLP information, whereas the second protocol stack supports differential signaling to communicate TLP information.
    Type: Application
    Filed: August 8, 2017
    Publication date: July 26, 2018
    Inventors: Bryan L. Spry, Marcus W. Song, Deepak M. Rangaraj, Avinash N. Ananthakrishnan, Robert J. Hayes, Aimee D. Wood, Brent R. Boswell
  • OPTIMIZED FC VARIANTS AND METHODS FOR THEIR GENERATION
    Publication number: 20180141997
    Abstract: The present invention relates to optimized Fc variants, methods for their generation, and antibodies and Fc fusions comprising optimized Fc variants.
    Type: Application
    Filed: June 26, 2017
    Publication date: May 24, 2018
    Inventors: Gregory Alan Lazar, Arthur J. Chirino, Wei Dang, John R. Desjarlais, Stephen K. Doberstein, Robert J. Hayes, Sher Bahadur Karki, Omid Vafa
  • Method, apparatus and system for configuring a protocol stack of an integrated circuit chip
    Patent number: 9734116
    Abstract: Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Peripheral Component Interconnect Express™ (PCIe™) specification. Configuration circuitry of the IC chip provides for configuration of a first protocol stack including the transaction layer, circuitry of the link layer and a first physical layer of the IC chip. The configuration circuitry further provides for an alternative configuration of a second protocol stack including the transaction layer, circuitry of the link layer and a second physical layer of the IC chip. In another embodiment, the first protocol stack supports single-ended signaling to communicate TLP information, whereas the second protocol stack supports differential signaling to communicate TLP information.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Bryan L. Spry, Marcus W. Song, Deepak M. Rangaraj, Avinash N. Ananthakrishnan, Robert J. Hayes, Aimee D. Wood, Adam E. Letendre, Brent R. Boswell
  • Optimized Fc variants and methods for their generation
    Patent number: 9714282
    Abstract: The present invention relates to optimized Fc variants, methods for their generation, and antibodies and Fc fusions comprising optimized Fc variants.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: July 25, 2017
    Assignee: Xencor, Inc.
    Inventors: Gregory Alan Lazar, Arthur J. Chirino, Wei Dang, John R. Desjarlais, Stephen K. Doberstein, Robert J. Hayes, Sher Bahadur Karki, Omid Vafa
  • OPTIMIZED Fc VARIANTS AND METHODS FOR THEIR GENERATION
    Publication number: 20160347837
    Abstract: The present invention relates to optimized Fc variants, methods for their generation, and antibodies and Fc fusions comprising optimized Fc variants.
    Type: Application
    Filed: May 27, 2016
    Publication date: December 1, 2016
    Inventors: Gregory Alan Lazar, Arthur J. Chirino, Wei Dang, John Desjarlais, Stephen K. Doberstein, Robert J. Hayes, Sher Bahadur Karki, Omid Vafa
  • OPTIMIZED Fc VARIANTS AND METHODS FOR THEIR GENERATION
    Publication number: 20160347825
    Abstract: The present invention relates to optimized Fc variants, methods for their generation, and antibodies and Fc fusions comprising optimized Fc variants.
    Type: Application
    Filed: May 27, 2016
    Publication date: December 1, 2016
    Inventors: Gregory Alan Lazar, Arthur J. Chirino, Wei Dang, John Desjarlais, Stephen K. Doberstein, Robert J. Hayes, Sher Bahadur Karki, Omid Vafa
  • OPTIMIZED Fc VARIANTS AND METHODS FOR THEIR GENERATION
    Publication number: 20160318993
    Abstract: The present invention relates to optimized Fc variants, methods for their generation, and antibodies and Fc fusions comprising optimized Fc variants.
    Type: Application
    Filed: May 6, 2016
    Publication date: November 3, 2016
    Inventors: Gregory Alan Lazar, Arthur J. Chirino, Wei Dang, John Desjarlais, Stephen K. Doberstein, Robert J. Hayes, Sher Bahadur Karki, Omid Vafa
  • Optimized FC variants and methods for their generation
    Patent number: 9353187
    Abstract: The present invention relates to optimized Fc variants, methods for their generation, and antibodies and Fc fusions comprising optimized Fc variants.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: May 31, 2016
    Assignee: Xencor, Inc.
    Inventors: Gregory Alan Lazar, Arthur J. Chirino, Wei Dang, John Desjarlais, Stephen K. Doberstein, Robert J. Hayes, Sher Bahadur Karki, Omid Vafa
  • Optimized Fc variants and methods for their generation
    Patent number: 9193798
    Abstract: The present invention relates to optimized Fc variants, methods for their generation, and antibodies and Fc fusions comprising optimized Fc variants.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: November 24, 2015
    Assignee: Xencor, Inc.
    Inventors: Gregory Alan Lazar, Arthur Chirino, Wei Dang, John Desjarlais, Stephen K. Doberstein, Robert J. Hayes, Sher Bahadur Karki, Omid Vafa
  • METHOD, APPARATUS AND SYSTEM FOR CONFIGURING A PROTOCOL STACK OF AN INTEGRATED CIRCUIT CHIP
    Publication number: 20150269108
    Abstract: Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Peripheral Component Interconnect Express™ (PCIe™) specification. Configuration circuitry of the IC chip provides for configuration of a first protocol stack including the transaction layer, circuitry of the link layer and a first physical layer of the IC chip. The configuration circuitry further provides for an alternative configuration of a second protocol stack including the transaction layer, circuitry of the link layer and a second physical layer of the IC chip. In another embodiment, the first protocol stack supports single-ended signaling to communicate TLP information, whereas the second protocol stack supports differential signaling to communicate TLP information.
    Type: Application
    Filed: March 13, 2015
    Publication date: September 24, 2015
    Inventors: Bryan L. Spry, Marcus W. Song, Deepak M. Rangaraj, Avinash N. Ananthakrishnan, Robert J. Hayes, Aimee D. Wood, Adam E. Letendre, Brent R. Boswell
  • OPTIMIZED Fc VARIANTS AND METHODS FOR THEIR GENERATION
    Publication number: 20150079082
    Abstract: The present invention relates to optimized Fc variants, methods for their generation, and antibodies and Fc fusions comprising optimized Fc variants.
    Type: Application
    Filed: November 21, 2014
    Publication date: March 19, 2015
    Inventors: Gregory Alan LAZAR, Arthur Chirino, Wei Dang, John Desjarlais, Stephen K. Doberstein, Robert J. Hayes, Sher Bahadur Karki, Omid Vafa
  • OPTIMIZED FC VARIANTS AND METHODS FOR THEIR GENERATION
    Publication number: 20140377256
    Abstract: The present invention relates to optimized Fc variants, methods for their generation, and antibodies and Fc fusions comprising optimized Fc variants.
    Type: Application
    Filed: May 23, 2014
    Publication date: December 25, 2014
    Applicant: Xencor, Inc.
    Inventors: Gregory Alan Lazar, Arthur J. Chirino, Wei Dang, John R. Desjarlais, Stephen K. Doberstein, Robert J. Hayes, Sher Bahadur Karki, Omid Vafa
  • OPTIMIZED Fc VARIANTS AND METHODS FOR THEIR GENERATION
    Publication number: 20140370021
    Abstract: The present invention relates to optimized Fc variants, methods for their generation, and antibodies and Fc fusions comprising optimized Fc variants.
    Type: Application
    Filed: June 14, 2013
    Publication date: December 18, 2014
    Applicant: Xencor, Inc.
    Inventors: Gregory Alan Lazar, Arthur J. Chirino, Wei Dang, John Desjarlais, Stephen K. Doberstein, Robert J. Hayes, Sher Bahadur Karki, Omid Vafa
  • Optimized Fc variants and methods for their generation
    Patent number: 8858937
    Abstract: The present invention relates to optimized Fc variants, methods for their generation, and antibodies and Fc fusions comprising optimized Fc variants.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: October 14, 2014
    Assignee: Xencor, Inc.
    Inventors: Gregory Alan Lazar, Arthur J. Chirino, Wei Dang, John Desjarlais, Stephen K. Doberstein, Robert J. Hayes, Sher Bahadur Karki, Omid Vafa
  • Optimized Fc variants and methods for their generation
    Patent number: 8809503
    Abstract: The present invention relates to optimized Fc variants, methods for their generation, and antibodies and Fc fusions comprising optimized Fc variants.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: August 19, 2014
    Assignee: Xencor, Inc.
    Inventors: Gregory Alan Lazar, Arthur J. Chirino, Wei Dang, John Desjarlais, Stephen K. Doberstein, Robert J. Hayes, Sher Bahadur Karki, Omid Vafa
  • Optimized fc variants and methods for their generation
    Patent number: 8734791
    Abstract: The present invention relates to optimized Fc variants, methods for their generation, and antibodies and Fc fusions comprising optimized Fc variants.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: May 27, 2014
    Assignee: Xencor, Inc.
    Inventors: Gregory Alan Lazar, Arthur J. Chirino, Wei Dang, John R. Desjarlais, Stephen K. Doberstein, Robert J. Hayes, Sher Bahadur Karki, Omid Vafa