Abstract: The ultraviolet absorption characteristics of a polymer material are modified by the addition of an ultraviolet absorbing dye to render it laser ablatable at a frequency at which the unmodified material is substantially non-laser ablatable.

Abstract: A high density interconnect structure incorporating a plurality of laminated dielectric layers is fabricated using a SPI/epoxy crosslinking copolymer blend adhesive in order to maintain the stability of the already fabricated structure during the addition of the later laminations while also maintaining the repairability of the high density interconnect structure.

Abstract: A high density interconnect structure incorporating a plurality of laminated dieletric layers is fabricated using thermoplastic adhesive layers of progressively lower glass transition temperature in order to maintain the stability of the already fabricated structure during the addition of the later laminations. This structure also facilitates the removal of only a portion of the high density interconnect structure where a fault in the system can be corrected in one of the upper layers of the high density interconnect structure.

Abstract: A method of removing components bonded to a substrate without damaging either the component-to-be-removed or adjacent components involves bonding a lifting member to an exposed surface of a component-to-be-removed with a bonding layer whose yielding temperature is above the yielding temperature of the bonding layer which bonds the component-to-be-removed to the substrate and then pulling the lifting member under conditions which cause the bond between the component and the substrate to yield. This component removal process enables post removal failure analysis to be performed on a faulty component and also allows a removed good component to be reused by preventing damage to the component being removed.

Abstract: A method for grounding or electrically biasing an integrated circuit chip without using a conductive die attach material comprises affixing the chips to a substrate using a thermoplastic polyimide adhesive. A metallization layer electrically connects the sides of the chips, which act as grounding surfaces, to a biased or grounded conductive layer on the substrate. The top surfaces of the integrated circuit chips which include the interconnection pads are protected against undesired metallization by a removable protective layer while the metallization layer is applied. Metal electroplated on the metallization layer serves the functions of a heat sink for the chip and a ground plane between chips.

Abstract: Semiconductor chips are protected from handling damage by formation of a polymer dielectric layer at least 2 microns thick on the chip surface before dicing or shortly after dicing. The polymer dielectric layer may be a thermoplastic material or a thermoset material.

Abstract: A copolymer blend of epoxy and polyimide is used as a dielectric layer in a multilayer interconnect structure. This copolymer blend is free of cracking and crazing, provides good interlayer adhesion and following fabrication, is stable at temperatures in excess of 200.degree. C. A preferred composition is a siloxane polyimide in combination with a cycloalaphatic epoxy.

Abstract: Interconnected integrated cirucits (16) packaged at a very high density are fabricated beginning with a plurality of substrates (50 or 400 or 500) where each substrate has metal edge contact sites (12 or 507). Several substrates are joined together in a stack (82 or 402 or 512) held together tightly by bolts (62) or by a thermoplastic adhesive (510). An interconnect pattern (250 or 423) electrically connects integrated circuits (16) on different substrates. Defective substrates are removable from the stack for repair by removing the bolts or by heating the adhesive to soften it sufficiently to allow removal of the individual substrate. The interconnect pattern, which is removed whenever a substrate is replaced, is reapplied after the removed substrate has been replaced.

Abstract: Conductive patterns may be formed on the surface of thermally inefficient substrates by depositing a uniform layer of metal thereover whose upper surface is substantially UV light absorbing followed by laser ablation of the deposited metal to leave the deposited metal only in the desired metal pattern. Thermally efficient substrates may be rendered thermally inefficient by the deposition of a thermally inefficient material thereon. That thermally inefficient material may be either electrically insulating or a metal. A two layer metallization comprising a first, thermally inefficient reactive metal and a second UV light absorbing metal is preferred. When disposed on a thermally inefficient substrate, this two layer metallization ablates reactively as the two layers burn off together. This laser ablation process substantially roughens the surface of polymer dielectrics and may be used to repair open traces in printed circuit structures.

Abstract: A method and apparatus are provided for disposing a polymer film on an irregularly-shaped substrate at relatively high temperatures. In particular, the method and apparatus of the present invention provide a system for the packaging of very large scale integrated circuit chips. The system of the present invention particularly solves problems associated with high temperature processing and problems associated with the highly irregular surfaces that result. Nonetheless, the resultant product is capable of being fashioned into circuit chip systems which are independently testable and which may be reconfigured after testing by removal of the polymer film itself.

Abstract: A method for grounding or electrically biasing an integrated circuit chip without using a conductive die attach material comprises affixing the chips to a substrate using a thermoplastic polyimide adhesive. A metallization layer electrically connects the sides of the chips, which act as grounding surfaces, to a biased or grounded conductive layer on the substrate. The top surfaces of the integrated circuit chips which include the interconnection pads are protected against undesired metallization by a removable protective layer while the metallization layer is applied. Metal electroplated on the metallization layer serves the functions of a heat sink for the chip and a ground plane between chips.

Abstract: Interconnected integrated circuits (16) packaged at a very high density are fabricated beginning with a plurality of substrates (50 or 400 or 500) where each substrate has metal edge contact sites (12 or 507). Several substrates are joined together in a stack (82 or 402 or 512) held together tightly by bolts (62) or by a thermoplastic adhesive (510). An interconnect pattern (250 or 423) electrically connects integrated circuits (16) on different substrates. Defective substrates are removable from the stack for repair by removing the bolts or by heating the adhesive to soften it sufficiently to allow removal of the individual substrate. The interconnect pattern, which is removed whenever a substrate is replaced, is reapplied after the removed substrate has been replaced.

Abstract: A laser capable of continuous wave operation is provided with a switching capability by including an electromagnetic transducer in its mirror adjustment system which is capable of moving the mirror sufficiently out of alignment ot interrupt laser action in the laser. In this manner, by switching the mirror between its aligned and misaligned conditions, the laser may be turned on and off without loss of output power and with pulse durations and duty cycles which are limited only by the ability of the electromagnetic transducer to move the mirror between its aligned and misaligned conditions. By providing separate transducers for both vertical and horizontal adjustment, alignment of the laser may be maintained electronically.

Abstract: The utilization of a removable overlay layer together with its associated metallization pattern, is used to effectively provide wafer scale integration for integrated circuit chips. The method and configuration of the present invention provide for the fabrication and testing of systems which are otherwise untestable. The present invention also permits integrated circuit systems to be tested in their final configuration in terms of speed and operating environment and the invention eliminates many of the problems associated with wafer or chip probes. The present invention also utilizes special test chips which are either temporarily or permanently affixed in an integrated circuit chip package.

Abstract: A method and apparatus are provided for disposing a polymer film on an irregularly-shaped substrate at relatively high temperatures. In particular, the method and apparatus of the present invention provide a system for the packaging of very large scale intergrated circuit chips. The system of the present invention particularly solves problems associated with high temperature processing and problems associated with the highly irregular surfaces that result. Nonetheless, the resultant product is capable of being fashioned into circuit chip systems which are independently testable and which may be reconfigured after testing by removal of the polymer film itself.

Abstract: A multichip integrated circuit package comprises a substrate to which is affixed one or more integrated circuit chips having interconnection pads. A polymer film overlying and bridging integrated circuit chips present is provided with a plurality of via openings to accommodate a layer of interconnection metallization which serves to connect various chips and chip pads within the interconnection pads disposed on the chips. A significant advantage of the packaging method and configuration of the present invention is the ability for the polymer film to be removed. This significantly improves testability and effectively provides wafer scale integration circuit packages which are free of problems associated with yield and testability.

Abstract: A package for interconnecting a plurality of integrated circuit chips into a functional unit comprising a multilayer substrate having ground and power conducting layers and a frame for holding the chips with their terminal pads on the side of the frame opposite the substrate. Power and ground terminal pads on the chips are coupled to the appropriate potentials via registering conductive feedthroughs passing through the frame and into the substrate into contact with appropriate power or conductive layers in the substrate. Signal pads on the chips are interconnected by means of a conductive layer which is located over the chips on the side of the frame opposite the substrate.

Abstract: The surface of a polymer dielectric layer is scanned repeatedly with a high energy continuous wave laser in a pattern to create via holes of desired size, shape and depth. This is followed by a short plasma etch. The via holes are produced at commercial production rates under direct computer control without use of masks and without damage to conductor material underlying the dielectric layer. A two-step technique usable to form a large hole to a partial depth in the dielectric layer and several smaller diameter holes within the large hole through the remainder of the dielectric layer depth allows formation of a large number of holes in a given area of a thick dielectric layer.

Abstract: The utilization of a removable overlay layer together with its associated metalization pattern, is used to effectively provide wafer scale integration for integrated circuit chips. The method and configuration of the present invention provide for the fabrication and testing of systems which are otherwise untestable. The present invention also permits integrated circuit systems to be tested in their final configuration in terms of speed and operating environment and the invention eliminates many of the problems associated with wafer or chip probes. The present invention also utilizes special test chips which are either temporarily or permanently affixed in an integrated circuit chip package.

Abstract: A simplified method of gaining access to, for the purpose of replacing, a defective integrated circuit chip situated in a high density interconnect (HDI) circuit (10) comprises heating the HDI circuit to a temperature at which the peel strength of an adhesive (16) bonding a polymer overlay layer (18) to the tops of integrated circuit chips (4, 6, and 8) positioned on a substrate (12) is reduced. The polymer overlay layer, which may comprise one or multiple layers, is then peeled from the chips. The adhesive is present in sufficient quantity to protect the chips. The adhesive is then dissolved by subjecting the substrate to different solvents of successively lower solubility for the adhesive. Metal divots (34) left on chip pads (36) are removed by selectively etching copper in the presence of ultrasonic agitation.