Patents by Inventor Robert J. Wojnarowski
Robert J. Wojnarowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 4866508Abstract: The present invention employs a high density interconnect method to take advantage of a packaging arrangement in which full customization of an integrated circuit chip package is providable in a single metallization layer. The integrated circuit chips are positioned to take full advantage of a wiring layer which includes a plurality of periodically interrupted conductor patterns. All of the customization is provided in a single layer which may be readily fabricated and produced in a single day making it possible for extremely rapid turn around time in the design of complex integrated circuit systems, particularly those constructed from readily available integrated circuit components including microprocessors, random access memory chips, decoders and the like. An integrated circuit is also disclosed for fully taking advantage of the capabilities of testing made available by the high density interconnect system.Type: GrantFiled: September 26, 1986Date of Patent: September 12, 1989Assignee: General Electric CompanyInventors: Charles W. Eichelberger, Kenneth B. Welles, II, Robert J. Wojnarowski
-
Patent number: 4842677Abstract: A dual layer resist configuration is employed for photopatterning high resolution conductive patterns on underlying polymeric or ceramic substrates, particularly substrates exhibiting surface roughness and non-planar design features such as channels, bosses and ridges. More particularly, a thin underlayer of ablatable photoabsorptive polymer is disposed on a metal coated substrate, after which a thicker layer of substantially transparent material is disposed over the polymer. A beam of laser energy, such as that produced by an ultraviolet excimer layer, is directed through the upper layer and is absorbed by the lower layer which is ablated and simultaneously removes the thick layer above it. This results in the ability to etch high resolution features on polymeric and other substrates, particularly copper coated polyetherimide circuit boards. The resist system is also applicable to VLSI wafers even though such wafers usually do not exhibit surface roughness on the scale generally considered herein.Type: GrantFiled: July 26, 1988Date of Patent: June 27, 1989Assignee: General Electric CompanyInventors: Robert J. Wojnarowski, Charles W. Eichelberger
-
Patent number: 4835704Abstract: An adaptive method and system are disclosed for providing high density interconnections of very large scale integrated circuits on a substrate. The procedure is performed in four basic steps: first an artwork representation for the interconnections of the integrated circuits is generated. This artwork representation is stored in a computer data base and assumes the integrated circuits to be at predetermined ideal locations and positions on the substrate. Second, using imaging, the actual positions of each integrated circuit on the substrate are determined. The actual positions of the integrated circuits are compared with their ideal positions to compute an offset and rotation for each integrated circuit on the substrate. Third, the computed offsets and rotations are then used to modify the artwork representation stored in the data base to account for the actual locations and positions of the integrated circuits on the substrate.Type: GrantFiled: December 29, 1986Date of Patent: May 30, 1989Assignee: General Electric CompanyInventors: Charles W. Eichelberger, Robert J. Wojnarowski, Kenneth B. Welles, II
-
Patent number: 4783695Abstract: A multichip integrated circuit package comprises a substrate to which is affixed one or more integrated circuit chips having interconnection pads. A polymer film overlying and bridging integrated circuit chips present is provided with a plurality of via openings to accommodate a layer of interconnection metallization which serves to connect various chips and chip pads within the interconnection pads disposed on the chips. A significant advantage of the packaging method and configuration of the present invention is the ability for the polymer film to be removed. This significantly improves testability and effectively provides wafer scale integration circuit packages which are free of problems associated with yield and testability.Type: GrantFiled: September 26, 1986Date of Patent: November 8, 1988Assignee: General Electric CompanyInventors: Charles W. Eichelberger, Robert J. Wojnarowski
-
Patent number: 4780177Abstract: A dual layer resist configuration is employed for photopatterning high resolution conductive patterns on underlying polymeric or ceramic substrates, particularly substrates exhibiting surface roughness and non-planar design features such as channels, bosses and ridges. More particularly, a thin underlayer of ablatable photoabsorptive polymer is disposed on a metal coated substrate, after which a thicker layer of substantially transparent material is disposed over the polymer. A beam of laser energy, such as that produced by an ultraviolet excimer laser, is directed through the upper layer and is absorbed by the lower layer which is ablated and simultaneously removes the thick layer above it. This results in the ability to etch high resolution features on polymeric and other substrates, particularly copper coated polyetherimide circuit boards. The resist system is also applicable to VLSI wafers even though such wafers usually do not exhibit surface roughness on the scale generally considered herein.Type: GrantFiled: February 5, 1988Date of Patent: October 25, 1988Assignee: General Electric CompanyInventors: Robert J. Wojnarowski, Charles W. Eichelberger
-
Patent number: 4770921Abstract: Self-shielding multi-layer circuit boards are produced utilizing augmentative replacement techniques.Type: GrantFiled: September 11, 1986Date of Patent: September 13, 1988Assignee: Insulating Materials IncorporatedInventors: Thomas P. Wacker, Charles W. Eichelberger, Robert J. Wojnarowski
-
Patent number: 4714516Abstract: A method for producing holes in a polymer film includes the steps of irradiating a spot on the film with a burst of focused laser energy at a level sufficient to damage the film without puncturing it and then subsequently plasma etching the irradiated film so as to remove the damaged portions. This method is particularly applicable to the formation of multichip integrated circuit packages in which a plurality of microcircuit chips are affixed to an underlying substrate which is coated with a polymer film covering the chips and the substrates. The holes are provided for the purpose of interconnecting the chips or making intrachip connections by means of a subsequently applied metallization layer.Type: GrantFiled: September 26, 1986Date of Patent: December 22, 1987Assignee: General Electric CompanyInventors: Charles W. Eichelberger, Robert J. Wojnarowski
-
Patent number: 4646152Abstract: Circuitry for enhancing the sharpness of bandwidth compressed television signals provides equalization in only the transmitter with no equalization required in the receiver. The transmitter includes a linear phase delay and edge peaking circuit, a low pass filter and an equalization circuit. The linear phase delay and edge peaking circuit includes a tapped delay line which provides weighted output signals for differential phase delays. The weighted output signals of the tapped delay line are differentially combined to provide a combined output signal. This combined output signal and a signal from the tapped delay line are supplied to a peaking circuit. A clamping circuit is connected to limit the amplitude of high level signals in the combined output signal so that small transitions are peaked to a greater degree than large transitions.Type: GrantFiled: February 1, 1985Date of Patent: February 24, 1987Assignee: General Electric CompanyInventors: Charles W. Eichelberger, Robert J. Wojnarowski, Theodore G. Mihran
-
Patent number: 4646151Abstract: A frame synchronizer having broad applicability in television systems is particularly adapted for use in a chrominance time-compressed, luminance bandwidth reduced television system. The frame synchronizer, which separates the composite video signal into its component parts and thereby minimizes the dynamic range required to digitize the signal, demodulates the chrominance signal into its quadrature components and separates the luminance signal. The synchronization signal in the composite video signal generates slave distribution signals and slave horizontal and vertical addresses. The separated chrominance quadrature components and the luminance signal are digitized and, along with the slave distribution signals and the slave horizontal and vertical addresses, are temporarily stored in first-in, first-out memories which provide independent buffering and thereby accommodate a high degree of mismatch between master and slave timing.Type: GrantFiled: February 1, 1985Date of Patent: February 24, 1987Assignee: General Electric CompanyInventors: Kenneth B. Welles, II, Robert J. Wojnarowski, Charles W. Eichelberger
-
Patent number: 4646149Abstract: An improved television bandwidth compression system allows two television programs to simultaneously utilize the bandwidth normally allowed for one television program. The basic bandwidth compression system comprises a transmitter which receives composite video signals from two program sources. The video processing circuitry of the transmitter provides an output signal wherein time-compressed chrominance information for the two program sources is sent on alternate lines during the normal horizontal retrace time and the luminance information for both program sources is sent during the active video time for each line. The receiver synthesizes a composite video signal of a selected program from the output signal transmitted from the transmitter.Type: GrantFiled: February 1, 1985Date of Patent: February 24, 1987Assignee: General Electric CompanyInventors: Robert J. Wojnarowski, Charles W. Eichelberger
-
Patent number: 4646135Abstract: A method and apparatus for bandwidth compression allows two television programs to simultaneously occupy the bandwidth normally allowed for one television program. The composite video signals from first and second program sources are separated into chrominance, luminance and synchronization component signals for each. The chrominance signals for each program source are compressed in time, and the sync pulse from one of the program sources is used to generate a narrow sync pulse. The luminance signal from the one program source modulates a carrier signal, and the luminance signal from the other program source modulates a subcarrier signal.Type: GrantFiled: February 1, 1985Date of Patent: February 24, 1987Assignee: General Electric CompanyInventors: Charles W. Eichelberger, Robert J. Wojnarowski
-
Patent number: 4571322Abstract: A method for providing insulated holes in a conductive substrate by first punching oversized holes in the substrate, then filling the holes with an insulator and then forming an aperture of a desired diameter, less than the diameter of the hole originally punched in the substrate, through the insulator to leave an annular sleeve of insulative material within each hole.Type: GrantFiled: July 5, 1985Date of Patent: February 18, 1986Assignee: General Electric CompanyInventors: Charles W. Eichelberger, Robert J. Wojnarowski, Abraham Auerbach
-
Patent number: 4528748Abstract: A method is described for batch-fabricating flat printed circuit boards and subsequently forming the circuit boards to a particular desired shape. In particular, a conductive substrate is coated with an insulating coating and conductors are fabricated thereon, with integrated circuit and chip resistor/capacitor parts being mounted to the fabricated conductor patterns. After part-mounting, the circuit board is bent to the desired shape.Type: GrantFiled: November 29, 1982Date of Patent: July 16, 1985Assignee: General Electric CompanyInventors: Charles W. Eichelberger, Robert J. Wojnarowski, Abraham Auerbach
-
Patent number: 4522888Abstract: A low-cost electrical conductor is prepared by applying a mixture of a metallic powder and a polymer on a substrate, curing the polymer, effecting an augmentation replacement reaction to replace some of the metallic powder with a more noble metal in such a way that the total volume of deposited metal at the surface exceeds that of the original metal powder replaced, and thereafter applying a dielectric material to selected areas of the conductor thus formed. Imperfections such as pin holes and screen marks can be eliminated by heating the dielectric material to cause a degree of flow. Multiple layer interconnected conductors can be prepared by reapplying the mixture of metallic powder and polymer such that a portion thereof contacts the first prepared conductor, curing the polymer and effecting an augmentation replacement reaction with a metal which is more noble than the powder metal and the replacement metal of the first conductor.Type: GrantFiled: May 25, 1983Date of Patent: June 11, 1985Assignee: General Electric CompanyInventors: Charles W. Eichelberger, Robert J. Wojnarowski
-
Patent number: 4495251Abstract: A microwave oven cabinet is constructed with plastic materials and has a low resistivity coating on the outside surfaces thereof, which coating is achieved by applying a mixture of a metallic powder and polymer on the surfaces and curing the polymer, followed by an augmentation replacement reaction being effected to replace some of the metallic powder with a more noble metal in such a way that the total volume on the surface of deposited metal exceeds that of the original metal powder replaced at the surface.Type: GrantFiled: February 14, 1983Date of Patent: January 22, 1985Assignee: General Electric CompanyInventors: Charles W. Eichelberger, Robert J. Wojnarowski, Peter I. Cohen
-
Patent number: 4487811Abstract: A low-cost conductor, e.g. a printed circuit, is prepared by applying a mixture of a metallic powder and polymer on a substrate and curing the polymer, followed by an augmentation replacement reaction being effected to replace some of the metallic powder with a more noble metal in such a way that the total volume of deposited metal on the surface exceeds that of the original metal powder at that surface. This procedure produces a contiguous layer of conducting metal on the substrate. The conductors thus formed can easily be soldered without leaching using conventional tin-lead solders.Type: GrantFiled: January 28, 1983Date of Patent: December 11, 1984Assignee: General Electric CompanyInventors: Charles W. Eichelberger, Robert J. Wojnarowski
-
Patent number: 4481404Abstract: In a cooking oven which is cleaned by pyrolyzation of soil within the oven cavity and has a smoke eliminator duct extending through the oven wall, with a smoke eliminator heater disposed adjacent to the duct inlet, a reducing gas sensor is mounted either adjacent to the oven end of the smoke eliminator duct or within the smoke eliminator duct near its discharge end. An electrical relay or microcomputer control is coupled between the gas sensor and the heater to initially heat the oven interior and to later deenergize the heater when the reducing gas sensor output indicates a desired oven condition. The oven heaters are temporarily deenergized when the gas sensor output indicate a smoke eliminator overload. If the gas sensor is mounted in the smoke eliminator duct, the smoke eliminator heater may be deenergized toward the end of the cleaning cycle, so that the effluent is not affected by the smoke eliminator heater before reaching the gas sensor.Type: GrantFiled: December 22, 1982Date of Patent: November 6, 1984Assignee: General Electric CompanyInventors: Charles E. Thomas, Robert J. Wojnarowski
-
Patent number: 4470883Abstract: Electrical conductors having enhanced resolution/spacing and adhesion characteristics are prepared by applying a mixture of a carbonyl-processed nickel powder and a polymer to a substrate, curing the polymer, and immersing the cured polymer pattern in an augmentative-replacement/electroplating bath, to effect an augmentative replacement reaction to form a contiguous layer of conducting metal on the substrate and thereafter electroplating an additional metal layer on the contiguous layer.Type: GrantFiled: May 2, 1983Date of Patent: September 11, 1984Assignee: General Electric CompanyInventors: Charles W. Eichelberger, Robert J. Wojnarowski
-
Patent number: 4466850Abstract: A one-time electrically-activated switch is composed of a cured polymeric binder which contains a powdered conductive material in an amount sufficient to establish particle-to-particle contact throughout the binder and in which the material powder particles have a non-conductive oxide surface sufficient to resist the flow of electricity below a given threshold. When a sufficiently high voltage is applied to the switch, the break-down voltage of the oxide layer is exceeded and avalanche current is permitted to flow. As a result, the oxide layer on the conductive particles breaks down along the break-down path and forms an irreversible low-impedance connection.Type: GrantFiled: January 24, 1983Date of Patent: August 21, 1984Assignee: General Electric CompanyInventors: Charles W. Eichelberger, Robert J. Wojnarowski
-
Patent number: 4441015Abstract: A novel cooking oven provides a plurality of elongated heating rods which are parallel to one another and surround the foodstuff to be cooked. The rods are energized sequentially by current flow controlled in magnitude and time to produce either black baking heat from the heating rods or infrared radiation from the heating rods by heating them to a red color. By sequentially heating the rods, the heat source in effect rotates around the foodstuff to be cooked to produce equal and even browning equivalent to that obtained by conventional rotisserie cooking in which the foodstuff is rotated relative to a stationary heat source. The oven may also be used in other heating modes such as pressurized cooking by containing the apparatus in a pressurized vessel with the heat sources consisting of inherent heat sources which will produce browning and crisping while heating in the pressurized mode.Type: GrantFiled: January 4, 1982Date of Patent: April 3, 1984Assignee: General Electric CompanyInventors: Charles W. Eichelberger, Robert J. Wojnarowski, William D. Ryckman, Jr.