Abstract: The present invention provides neurotoxicity and developmental neurotoxicity screening methods employing primary cultured neurons from Drosophila.

Abstract: A system and method for fabricating a mandrel wound antenna are provided. The method includes securing a first end of a wire to a first portion of a mandrel tool, where the mandrel tool includes a faceplate supporting a plurality of posts, and the posts arranged and disposed to define non-overlapping circumferential patterns. The method also includes wrapping the wire around outer peripheries of the plurality of posts to form non-overlapping wire coils around the plurality of circumferential patterns to provide an antenna. The method further includes securing a second end of the wire to a second portion of the mandrel tool, cutting the wire in proximity to the second end, attaching the antenna to a substrate separate from the faceplate, and detaching the antenna from the faceplate.

Abstract: The present invention provides neurotoxicity and developmental neurotoxicity screening methods employing primary cultured neurons from Drosophila.

Abstract: A smart card inlay and method for assembling the same are provided. The method includes attaching a first trace to a substrate, attaching a second trace to the substrate, attaching an antenna wire to the substrate, coupling a first end of the antenna wire to a first area of the first trace, and coupling a second end of the antenna wire to a first area of the second trace. A second area of the first trace and a second area of the second trace are configured to be coupled to an integrated circuit (IC) or IC module, and the first area of the first trace is located away from the second area of the first trace and the first area of the second trace is located away from the second area of the second trace.

Abstract: A system and method for fabricating a mandrel wound antenna are provided. The method includes securing a first end of a wire to a first portion of a mandrel tool, where the mandrel tool includes a faceplate supporting a plurality of posts, and the posts arranged and disposed to define non-overlapping circumferential patterns. The method also includes wrapping the wire around outer peripheries of the plurality of posts to form non-overlapping wire coils around the plurality of circumferential patterns to provide an antenna. The method further includes securing a second end of the wire to a second portion of the mandrel tool, cutting the wire in proximity to the second end, attaching the antenna to a substrate separate from the faceplate, and detaching the antenna from the faceplate.

Abstract: A smart card inlay and method for assembling the same are provided. The method includes attaching a first trace to a substrate, attaching a second trace to the substrate, attaching an antenna wire to the substrate, coupling a first end of the antenna wire to a first area of the first trace, and coupling a second end of the antenna wire to a first area of the second trace. A second area of the first trace and a second area of the second trace are configured to be coupled to an integrated circuit (IC) or IC module, and the first area of the first trace is located away from the second area of the first trace and the first area of the second trace is located away from the second area of the second trace.

Abstract: A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C.

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).

Abstract: A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.

Abstract: The present invention provides an interconnect structure, a method of manufacture therefore, and a method for manufacturing an integrated circuit including the same. The method for forming the interconnect structure, among other steps, includes subjecting a first portion (510) of a substrate (220) to a first etch process, the first etch process designed to etch at a first entry angle (?1), and subjecting a second portion (610) of the substrate (220) to a second different etch process, the second different etch process designed to etch at a second lesser entry angle (?2).

Abstract: In accordance with the present teachings, semiconductor devices and methods of making semiconductor devices and dielectric stack in an integrated circuit are provided. The method of forming a dielectric stack in an integrated circuit can include providing a semiconductor structure including one or more copper interconnects and forming an etch stop layer over the semiconductor structure in a first processing chamber. The method can also include forming a thin silicon oxide layer over the etch stop layer in the first processing chamber and forming an ultra low-k dielectric layer over the thin silicon oxide layer in a second processing chamber, wherein forming the thin silicon oxide layer improves adhesion between the etch stop layer and the ultra low-k dielectric as compared to a dielectric stack that is devoid of the thin silicon oxide layer between the etch stop layer and the ultra low-k dielectric.

Abstract: The present invention provides a process for improving the hardness and/or modulus of elasticity of a dielectric layer and a method for manufacturing an integrated circuit. The process for improving the hardness and/or modulus of elasticity of a dielectric layer, among other steps, includes providing a dielectric layer having a hardness and a modulus of elasticity, and subjecting the dielectric layer to an energy beam, thereby causing the hardness or modulus of elasticity to increase in value.

Abstract: A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C.

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).

Abstract: In accordance with the present teachings, semiconductor devices and methods of making semiconductor devices and dielectric stack in an integrated circuit are provided. The method of forming a dielectric stack in an integrated circuit can include providing a semiconductor structure including one or more copper interconnects and forming an etch stop layer over the semiconductor structure in a first processing chamber. The method can also include forming a thin silicon oxide layer over the etch stop layer in the first processing chamber and forming an ultra low-k dielectric layer over the thin silicon oxide layer in a second processing chamber, wherein forming the thin silicon oxide layer improves adhesion between the etch stop layer and the ultra low-k dielectric as compared to a dielectric stack that is devoid of the thin silicon oxide layer between the etch stop layer and the ultra low-k dielectric.

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).

Abstract: Gyroscopic Torque Induced Unidirectional Engine is a combination of five engines with a center bi-directional torque motor controlling torque speed, direction and timing of both upper and lower pair-sets of Gyro engines attached to center motors upper and lower drive axles. By electronically manipulating the power to the bi-directional torque motor and the gyros', the force factors are controlled between the upper and lower sets. With the first phase of upper gyros operations repeated by the second phase of lower gyros inducing torques speeds and directions 180 degrees out of phase with the upper gyros. Timing is synchronized for gyros to support one another through its push-reach, pull-reach, “crawl” through space like a twisting caterpillar to obtain an overall combined total engine thrust in a single direction overcoming accelerated Gravity's weight plus POWER to create engine speed in any of the controlled directions.

Abstract: A semiconductor device is fabricated with energy based process(es) that alter etch rates for dielectric layers within damascene processes. A first interconnect layer is formed over a semiconductor body. A first dielectric layer is formed over the first interconnect layer. An etch rate of the first dielectric layer is altered. A second dielectric layer is formed on the first dielectric layer. An etch rate of the second dielectric layer is then altered. A trench etch is performed to form a trench cavity within the second dielectric layer. A via etch is performed to form a via cavity within the first dielectric layer. The cavities are filled with conductive material and then planarized to remove excess fill material.

Abstract: In accordance with the invention, there are semiconductor devices and methods for making semiconductor devices and film stacks in an integrated circuits. The method of making a semiconductor device can comprise forming a semiconductor structure comprising at least one copper interconnect, forming an etch stop bi-layer comprising a first layer and a second layer, wherein the first layer comprising silicon nitride is disposed over the semiconductor structure comprising at least one copper interconnect, and the second layer comprising silicon oxy-carbide is disposed over the first layer, and depositing a dielectric layer over the etch stop bi-layer.

Abstract: A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.